Merge branch 'master' of git://88.191.163.10/u-boot-arm

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 69b848740b8b62389456b58d00a411bdc33accac..8150bffb8ce60b5c1947f65e5554598b24316f6d 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -4,23 +4,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -32,6 +16,8 @@
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
 #include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
 
 struct scu_regs {
        u32     ctrl;
@@ -172,8 +158,8 @@ void enable_caches(void)
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-       struct fuse_bank *bank = &iim->bank[4];
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[4];
        struct fuse_bank4_regs *fuse =
                        (struct fuse_bank4_regs *)bank->fuse_regs;
 
@@ -228,3 +214,44 @@ const struct boot_mode soc_boot_modes[] = {
 void s_init(void)
 {
 }
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+       struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+       u8 reg;
+       reg = readb(&hdmi->phy_conf0);
+       reg |= HDMI_PHY_CONF0_PDZ_MASK;
+       writeb(reg, &hdmi->phy_conf0);
+       udelay(3000);
+       reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+       writeb(reg, &hdmi->phy_conf0);
+       udelay(3000);
+       reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+       writeb(reg, &hdmi->phy_conf0);
+       writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+       int reg;
+
+       /* Turn on HDMI PHY clock */
+       reg = readl(&mxc_ccm->CCGR2);
+       reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+                MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+       writel(reg, &mxc_ccm->CCGR2);
+       writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+       reg = readl(&mxc_ccm->chsccdr);
+       reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+                MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+                MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+       reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+                << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+                |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+                << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->chsccdr);
+}
+#endif