imx: mx6: Fixed AIPS3 base address issue

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5cf472d24f3393ea8aa8e0bdfb17f27230983529..ee035c576e695e9c4afceb379d31e087cdb60b48 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,6 +8,11 @@
  */
 
 #include <common.h>
+#include <stdbool.h>
+#include <dm.h>
+#include <div64.h>
+#include <ipu.h>
+#include <imx_thermal.h>
 #include <asm/armv7.h>
 #include <asm/bootm.h>
 #include <asm/pl310.h>
@@ -17,17 +22,10 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/regs-ocotp.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
-#include <stdbool.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/bootm.h>
-#include <dm.h>
-#include <imx_thermal.h>
-#include <div64.h>
-#include <ipu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -128,14 +126,14 @@ u32 __weak get_board_rev(void)
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
        struct aipstz_regs *aips3;
 #endif
 
-       aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
-       aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX
-       aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+       aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
+       aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
+#ifdef CONFIG_SOC_MX6SX
+       aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
 #endif
 
        /*
@@ -163,7 +161,7 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
         * not forced to user-mode.
@@ -452,7 +450,7 @@ static void clear_mmdc_ch_mask(void)
        writel(0, &mxc_ccm->ccdr);
 }
 
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 static void set_preclk_from_osc(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -480,7 +478,7 @@ int arch_cpu_init(void)
                set_ahb_rate(132000000);
 
                /* Set perclk to source from OSC 24MHz */
-#if defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_MX6SL)
        set_preclk_from_osc();
 #endif
 
@@ -677,7 +675,7 @@ void v7_outer_cache_enable(void)
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
        unsigned int val;
 
-#if defined CONFIG_MX6SL
+#if defined CONFIG_SOC_MX6SL
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        val = readl(&iomux->gpr[11]);
        if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
@@ -708,7 +706,7 @@ void v7_outer_cache_enable(void)
         * double linefill feature. This is the default behavior.
         */
 
-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_MX6Q
        val |= 0x40800000;
 #endif
        writel(val, &pl310->pl310_prefetch_ctrl);