Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / clocks-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 88e5336850cfbab0698ad65a90fbf86b357d8121..2b955c7c006b2a2d9541d5ac1e8c5c4ddf76f6cb 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -55,11 +55,12 @@ const u32 sys_clk_array[8] = {
        26000000,              /* 26 MHz */
        27000000,              /* 27 MHz */
        38400000,              /* 38.4 MHz */
+       20000000,               /* 20 MHz */
 };
 
 static inline u32 __get_sys_clk_index(void)
 {
-       u32 ind;
+       s8 ind;
        /*
         * For ES1 the ROM code calibration of sys clock is not reliable
         * due to hw issue. So, use hard-coded value. If this value is not
@@ -73,6 +74,13 @@ static inline u32 __get_sys_clk_index(void)
                /* SYS_CLKSEL - 1 to match the dpll param array indices */
                ind = (readl((*prcm)->cm_sys_clksel) &
                        CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+               /*
+                * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
+                * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
+                * NUM_SYS_CLK. So considering the last 3 bits as the index
+                * for the dpll param array.
+                */
+               ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
        }
        return ind;
 }
@@ -103,10 +111,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params)
                writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
        if (params->m7_h14 >= 0)
                writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
+       if (params->h21 >= 0)
+               writel(params->h21, &dpll_regs->cm_div_h21_dpll);
        if (params->h22 >= 0)
                writel(params->h22, &dpll_regs->cm_div_h22_dpll);
        if (params->h23 >= 0)
                writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+       if (params->h24 >= 0)
+               writel(params->h24, &dpll_regs->cm_div_h24_dpll);
 }
 
 static inline void do_bypass_dpll(u32 const base)
@@ -197,12 +209,25 @@ const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
 #endif
 }
 
+static const struct dpll_params *get_ddr_dpll_params
+                       (struct dplls const *dpll_data)
+{
+       u32 sysclk_ind = get_sys_clk_index();
+
+       if (!dpll_data->ddr)
+               return NULL;
+       return &dpll_data->ddr[sysclk_ind];
+}
+
 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
                                u8 lock, char *dpll)
 {
        u32 temp, M, N;
        struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
 
+       if (!params)
+               return;
+
        temp = readl(&dpll_regs->cm_clksel_dpll);
 
        if (check_for_lock(base)) {
@@ -319,11 +344,6 @@ void configure_mpu_dpll(void)
                        CM_CLKSEL_DCC_EN_MASK);
        }
 
-       setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
-               MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
-       setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
-               MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
-
        params = get_mpu_dpll_params(*dplls_data);
 
        do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
@@ -398,6 +418,9 @@ static void setup_dplls(void)
 #ifdef CONFIG_USB_EHCI_OMAP
        setup_usb_dpll();
 #endif
+       params = get_ddr_dpll_params(*dplls_data);
+       do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
+                     params, DPLL_LOCK, "ddr");
 }
 
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@@ -589,7 +612,7 @@ void freq_update_core(void)
 
        /*
         * Putting EMIF in HW_AUTO is seen to be causing issues with
-        * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
+        * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
         * in OMAP5430 ES1.0 silicon
         */
        if (omap_rev != OMAP5430_ES1_0) {
@@ -636,7 +659,7 @@ void setup_clocks_for_console(void)
                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 
-       clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
+       clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
                        MODULE_CLKCTRL_MODULEMODE_MASK,
                        MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
                        MODULE_CLKCTRL_MODULEMODE_SHIFT);