Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / clocks-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 9c75c13c9f0a8f925ea2f877fecfee6dd9c8fa6d..ab0c5680f546ba3c068a56e21ecd2754df007e21 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -11,23 +11,7 @@
  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
  *     Rajendra Nayak <rnayak@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <i2c.h>
@@ -50,13 +34,12 @@
 
 const u32 sys_clk_array[8] = {
        12000000,              /* 12 MHz */
-       13000000,              /* 13 MHz */
+       20000000,               /* 20 MHz */
        16800000,              /* 16.8 MHz */
        19200000,              /* 19.2 MHz */
        26000000,              /* 26 MHz */
        27000000,              /* 27 MHz */
        38400000,              /* 38.4 MHz */
-       20000000,               /* 20 MHz */
 };
 
 static inline u32 __get_sys_clk_index(void)
@@ -75,13 +58,6 @@ static inline u32 __get_sys_clk_index(void)
                /* SYS_CLKSEL - 1 to match the dpll param array indices */
                ind = (readl((*prcm)->cm_sys_clksel) &
                        CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
-               /*
-                * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
-                * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
-                * NUM_SYS_CLK. So considering the last 3 bits as the index
-                * for the dpll param array.
-                */
-               ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
        }
        return ind;
 }
@@ -220,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params
        return &dpll_data->ddr[sysclk_ind];
 }
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+static const struct dpll_params *get_gmac_dpll_params
+                       (struct dplls const *dpll_data)
+{
+       u32 sysclk_ind = get_sys_clk_index();
+
+       if (!dpll_data->gmac)
+               return NULL;
+       return &dpll_data->gmac[sysclk_ind];
+}
+#endif
+
 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
                                u8 lock, char *dpll)
 {
@@ -422,6 +410,12 @@ static void setup_dplls(void)
        params = get_ddr_dpll_params(*dplls_data);
        do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
                      params, DPLL_LOCK, "ddr");
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+       params = get_gmac_dpll_params(*dplls_data);
+       do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
+                     DPLL_LOCK, "gmac");
+#endif
 }
 
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@@ -441,6 +435,12 @@ static void setup_non_essential_dplls(void)
        params = get_abe_dpll_params(*dplls_data);
 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
        abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+       if (omap_revision() == DRA752_ES1_0)
+               /* Select the sys clk for dpll_abe */
+               clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
+                               CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+                               CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
 #else
        abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
        /*
@@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
 
        val = optimize_vcore_voltage(&vcores->iva);
        do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
-
-        if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
-               /* Configure LDO SRAM "magic" bits */
-               writel(2, (*prcm)->prm_sldo_core_setup);
-               writel(2, (*prcm)->prm_sldo_mpu_setup);
-               writel(2, (*prcm)->prm_sldo_mm_setup);
-       }
 }
 
 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)