Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / emif-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 7c2352c7fd5a22308e71bb4f995b9e4adef27729..30dcf1b0b04ec1112a8dead33762c289c8915001 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -31,6 +31,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
+#include <linux/compiler.h>
 
 void set_lpmode_selfrefresh(u32 base)
 {
@@ -140,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs)
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-       u32 *ext_phy_ctrl_base = 0;
-       u32 *emif_ext_phy_ctrl_base = 0;
-       u32 i = 0;
 
        /* Not NVM */
        clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -160,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
        writel(regs->sdram_config_init, &emif->emif_sdram_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 
-       ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-       emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-       if (omap_revision() >= OMAP5430_ES1_0) {
-               /* Configure external phy control timing registers */
-               for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-                       writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-                       /* Update shadow registers */
-                       writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-               }
-
-               /*
-                * external phy 6-24 registers do not change with
-                * ddr frequency
-                */
-               for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
-                       writel(ext_phy_ctrl_const_base[i],
-                                               emif_ext_phy_ctrl_base++);
-                       /* Update shadow registers */
-                       writel(ext_phy_ctrl_const_base[i],
-                                               emif_ext_phy_ctrl_base++);
-               }
-       }
+       do_ext_phy_settings(base, regs);
 
        do_lpddr2_init(base, CS0);
        if (regs->sdram_config & EMIF_REG_EBANK_MASK)
@@ -194,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
        /* Enable refresh now */
        clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 
+       }
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
 }
 
 void emif_update_timings(u32 base, const struct emif_regs *regs)