Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap-common / emif-common.c

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 8864abc16e4eee4ec755046c88da30194cf1be42..cdb443972175e6b1b0166007ab3c0a0f487e90c6 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -123,11 +123,13 @@ void emif_reset_phy(u32 base)
 static void do_lpddr2_init(u32 base, u32 cs)
 {
        u32 mr_addr;
+       const struct lpddr2_mr_regs *mr_regs;
 
+       get_lpddr2_mr_regs(&mr_regs);
        /* Wait till device auto initialization is complete */
        while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
                ;
-       set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+       set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
        /*
         * tZQINIT = 1 us
         * Enough loops assuming a maximum of 2GHz
@@ -135,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs)
 
        sdelay(2000);
 
-       if (omap_revision() >= OMAP5430_ES1_0)
-               set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
-       else
-               set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
-       set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+       set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+       set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 
        /*
         * Enable refresh along with writing MR2
         * Encoding of RL in MR2 is (RL - 2)
         */
        mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
-       set_mr(base, cs, mr_addr, RL_FINAL - 2);
+       set_mr(base, cs, mr_addr, mr_regs->mr2);
 
-       if (omap_revision() >= OMAP5430_ES1_0)
-               set_mr(base, cs, LPDDR2_MR3, 0x1);
+       if (mr_regs->mr3 > 0)
+               set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 }
 
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
@@ -268,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 static void ddr3_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-       u32 *ext_phy_ctrl_base = 0;
-       u32 *emif_ext_phy_ctrl_base = 0;
-       u32 i = 0;
 
        /*
         * Set SDRAM_CONFIG and PHY control registers to locked frequency
@@ -290,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
        writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-       ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-       emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-       /* Configure external phy control timing registers */
-       for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-               writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-               /* Update shadow registers */
-               writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-       }
-
-       /*
-        * external phy 6-24 registers do not change with
-        * ddr frequency
-        */
-       for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
-               writel(ddr3_ext_phy_ctrl_const_base[i],
-                                       emif_ext_phy_ctrl_base++);
-               /* Update shadow registers */
-               writel(ddr3_ext_phy_ctrl_const_base[i],
-                                       emif_ext_phy_ctrl_base++);
-       }
+       do_ext_phy_settings(base, regs);
 
        /* enable leveling */
        writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
@@ -680,20 +655,27 @@ static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
        return phy;
 }
 
-static u32 get_emif_mem_size(struct emif_device_details *devices)
+static u32 get_emif_mem_size(u32 base)
 {
        u32 size_mbytes = 0, temp;
+       struct emif_device_details dev_details;
+       struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+       u32 emif_nr = emif_num(base);
 
-       if (!devices)
-               return 0;
+       emif_reset_phy(base);
+       dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+                                               &cs0_dev_details);
+       dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+                                               &cs1_dev_details);
+       emif_reset_phy(base);
 
-       if (devices->cs0_device_details) {
-               temp = devices->cs0_device_details->density;
+       if (dev_details.cs0_device_details) {
+               temp = dev_details.cs0_device_details->density;
                size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
        }
 
-       if (devices->cs1_device_details) {
-               temp = devices->cs1_device_details->density;
+       if (dev_details.cs1_device_details) {
+               temp = dev_details.cs1_device_details->density;
                size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
        }
        /* convert to bytes */
@@ -1065,13 +1047,9 @@ static void do_sdram_init(u32 base)
        /* Return if no devices on this EMIF */
        if (!dev_details.cs0_device_details &&
            !dev_details.cs1_device_details) {
-               emif_sizes[emif_nr - 1] = 0;
                return;
        }
 
-       if (!in_sdram)
-               emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
-
        /*
         * Get device timings:
         * - Default timings specified by JESD209-2 if
@@ -1109,9 +1087,6 @@ void emif_post_init_config(u32 base)
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
        u32 omap_rev = omap_revision();
 
-       if (omap_rev == OMAP5430_ES1_0)
-               return;
-
        /* reset phy on ES2.0 */
        if (omap_rev == OMAP4430_ES2_0)
                emif_reset_phy(base);
@@ -1136,8 +1111,8 @@ void dmm_init(u32 base)
        mapped_size = 0;
        section_cnt = 3;
        sys_addr = CONFIG_SYS_SDRAM_BASE;
-       emif1_size = emif_sizes[0];
-       emif2_size = emif_sizes[1];
+       emif1_size = get_emif_mem_size(EMIF1_BASE);
+       emif2_size = get_emif_mem_size(EMIF2_BASE);
        debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
 
        if (!emif1_size && !emif2_size)
@@ -1219,7 +1194,7 @@ void dmm_init(u32 base)
        writel(lisa_map_regs->dmm_lisa_map_0,
                &hw_lisa_map_regs->dmm_lisa_map_0);
 
-       if (omap_revision() >= OMAP4460_ES1_0) {
+       if (lisa_map_regs->is_ma_present) {
                hw_lisa_map_regs =
                    (struct dmm_lisa_map_regs *)MA_BASE;
 
@@ -1289,9 +1264,9 @@ void sdram_init(void)
 
        if (!(in_sdram || warm_reset())) {
                if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
-                       bypass_dpll(&prcm->cm_clkmode_dpll_core);
+                       bypass_dpll((*prcm)->cm_clkmode_dpll_core);
                else
-                       writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+                       writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
        }
 
        if (!in_sdram)