omap_gpmc: change nandecc command

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap3 / board.c

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 52196c8f66e91be062d6aa55383c6cb0a8a99c4e..b72fadc2575a4f4facc2affe4c0319e8de73a4af 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -33,22 +33,26 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
-#include <asm/spl.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
 #include <linux/compiler.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
+#endif
 
 static const struct gpio_bank gpio_bank_34xx[6] = {
        { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -94,11 +98,11 @@ int board_mmc_init(bd_t *bis)
 {
        switch (spl_boot_device()) {
        case BOOT_DEVICE_MMC1:
-               omap_mmc_init(0, 0, 0);
+               omap_mmc_init(0, 0, 0, -1, -1);
                break;
        case BOOT_DEVICE_MMC2:
        case BOOT_DEVICE_MMC2_2:
-               omap_mmc_init(1, 0, 0);
+               omap_mmc_init(1, 0, 0, -1, -1);
                break;
        }
        return 0;
@@ -106,7 +110,7 @@ int board_mmc_init(bd_t *bis)
 
 void spl_board_init(void)
 {
-#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
        gpmc_init();
 #endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
@@ -252,6 +256,8 @@ void s_init(void)
 #endif
 
 #ifdef CONFIG_SPL_BUILD
+       gd = &gdata;
+
        preloader_console_init();
 
        timer_init();
@@ -322,14 +328,25 @@ void abort(void)
  *****************************************************************************/
 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-       if (argc != 2)
+       if (argc < 2 || argc > 3)
                goto usage;
-       if (strncmp(argv[1], "hw", 2) == 0)
-               omap_nand_switch_ecc(1);
-       else if (strncmp(argv[1], "sw", 2) == 0)
-               omap_nand_switch_ecc(0);
-       else
+
+       if (strncmp(argv[1], "hw", 2) == 0) {
+               if (argc == 2) {
+                       omap_nand_switch_ecc(1, 1);
+               } else {
+                       if (strncmp(argv[2], "hamming", 7) == 0)
+                               omap_nand_switch_ecc(1, 1);
+                       else if (strncmp(argv[2], "bch8", 4) == 0)
+                               omap_nand_switch_ecc(1, 8);
+                       else
+                               goto usage;
+               }
+       } else if (strncmp(argv[1], "sw", 2) == 0) {
+               omap_nand_switch_ecc(0, 0);
+       } else {
                goto usage;
+       }
 
        return 0;
 
@@ -339,9 +356,13 @@ usage:
 }
 
 U_BOOT_CMD(
-       nandecc, 2, 1,  do_switch_ecc,
+       nandecc, 3, 1,  do_switch_ecc,
        "switch OMAP3 NAND ECC calculation algorithm",
-       "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+       "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
+       " 8-bit BCH\n"
+       "                           ecc calculation (second parameter may"
+       " be omitted).\n"
+       "nandecc sw               - Switch to NAND software ecc algorithm."
 );
 
 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
@@ -406,19 +427,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
        }
 }
 
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
-       u32 acr;
-
-       /* Read ACR */
-       asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-       acr &= ~clear_bits;
-       acr |= set_bits;
-
-       /* Write ACR - affects non-secure banked bits */
-       asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
 static void omap3_setup_aux_cr(void)
 {
        /* Workaround for Cortex-A8 errata: #454179 #430973
@@ -432,6 +440,19 @@ static void omap3_setup_aux_cr(void)
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+       u32 acr;
+
+       /* Read ACR */
+       asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+       acr &= ~clear_bits;
+       acr |= set_bits;
+
+       /* Write ACR - affects non-secure banked bits */
+       asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
 /* Invalidate the entire L2 cache from secure mode */
 static void omap3_invalidate_l2_cache_secure(void)
 {
@@ -472,7 +493,7 @@ void omap3_outer_cache_disable(void)
         */
        omap3_update_aux_cr(0, 0x2);
 }
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -480,4 +501,4 @@ void enable_caches(void)
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }
-#endif
+#endif /* !CONFIG_SYS_DCACHE_OFF */