Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap3 / clock.c

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 2238c52e3bec7c23d0c97546cba293788d2db7de..81cc8597803e99a65ef26e56faf1729f44217490 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -27,7 +27,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/clocks_omap3.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
@@ -278,6 +278,25 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
        wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 }
 
+static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
+{
+       struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+       dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
+
+       /* Moving it to the right sysclk base */
+       ptr = ptr + clk_index;
+
+       /* PER2 DPLL (DPLL5) */
+       sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+       wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+       sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+       sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+       sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+       sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);   /* FREQSEL */
+       sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
+       wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
 {
        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -380,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
                /* L3 */
                sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
                /* GFX */
-               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV_36X);
                /* RESET MGR */
                sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
@@ -553,6 +572,22 @@ void prcm_init(void)
        }
 
        if (get_cpu_family() == CPU_OMAP36XX) {
+               /*
+                * In warm reset conditions on OMAP36xx/AM/DM37xx
+                * the rom code incorrectly sets the DPLL4 clock
+                * input divider to /6.5. Section 3.5.3.3.3.2.1 of
+                * the AM/DM37x TRM explains that the /6.5 divider
+                * is used only when the input clock is 13MHz.
+                *
+                * If the part is in this cpu family *and* the input
+                * clock *is not* 13 MHz, then reset the DPLL4 clock
+                * input divider to /1 as it should never set to /6.5
+                * in this case.
+                */
+               if (sys_clkin_sel != 1) /* 13 MHz */
+                       /* Bit 8: DPLL4_CLKINP_DIV */
+                       sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+
                /* Unlock MPU DPLL (slows things down, and needed later) */
                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
                wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
@@ -560,6 +595,7 @@ void prcm_init(void)
 
                dpll3_init_36xx(0, clk_index);
                dpll4_init_36xx(0, clk_index);
+               dpll5_init_34xx(0, clk_index);
                iva_init_36xx(0, clk_index);
                mpu_init_36xx(0, clk_index);
 
@@ -587,7 +623,10 @@ void prcm_init(void)
 
                dpll3_init_34xx(sil_index, clk_index);
                dpll4_init_34xx(sil_index, clk_index);
-               iva_init_34xx(sil_index, clk_index);
+               dpll5_init_34xx(sil_index, clk_index);
+               if (get_cpu_family() != CPU_AM35XX)
+                       iva_init_34xx(sil_index, clk_index);
+
                mpu_init_34xx(sil_index, clk_index);
 
                /* Lock MPU DPLL to set frequency */
@@ -603,6 +642,26 @@ void prcm_init(void)
        sdelay(5000);
 }
 
+/*
+ * Enable usb ehci uhh, tll clocks
+ */
+void ehci_clocks_enable(void)
+{
+       struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+       /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+       sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+       /*
+        * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+        * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+        */
+       sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+       /* Enable USBTTL_ICLK */
+       sr32(&prcm_base->iclken3_core, 2, 1, 1);
+       /* Enable USBTTL_FCLK */
+       sr32(&prcm_base->fclken3_core, 2, 1, 1);
+}
+
 /******************************************************************************
  * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
  *****************************************************************************/
@@ -654,7 +713,9 @@ void per_clocks_enable(void)
        /* Enable the ICLK for 32K Sync Timer as its used in udelay */
        sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
 
-       sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+       if (get_cpu_family() != CPU_AM35XX)
+               sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
+
        sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
        sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
        sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
@@ -662,8 +723,10 @@ void per_clocks_enable(void)
        sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
        sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
        sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
-       sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
-       sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+       if (get_cpu_family() != CPU_AM35XX) {
+               sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
+               sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
+       }
        sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
        sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);