ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index e4abb25fc2430acc2917dd9a66a72c5de7092ebc..e0ee23f3d1fa3f8d5801ba0eb7a3896e7373c08b 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,9 +460,12 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio6_clkctrl,
                (*prcm)->cm_l4per_gpio7_clkctrl,
                (*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
                (*prcm)->cm_l3init_ocp2scp1_clkctrl,
                (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+#endif
 #endif
                0
        };
@@ -495,7 +498,7 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
        /* Enable 960 MHz clock for dwc3 */
        setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
                     OPTFCLKEN_REFCLK960M);
@@ -503,6 +506,19 @@ void enable_basic_clocks(void)
        /* Enable 32 KHz clock for dwc3 */
        setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
                     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+       /* Enable 960 MHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
+                    OPTFCLKEN_REFCLK960M);
+
+       /* Enable 32 KHz clock for dwc3 */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
+                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+       /* Enable 60 MHz clock for USB2PHY2 */
+       setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
+                    L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
+#endif
 #endif
 
        /* Set the correct clock dividers for mmc */
@@ -534,6 +550,9 @@ void enable_basic_clocks(void)
 void enable_basic_uboot_clocks(void)
 {
        u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_clkstctrl,
+#endif
                0
        };
 
@@ -547,7 +566,11 @@ void enable_basic_uboot_clocks(void)
                (*prcm)->cm_l4per_i2c2_clkctrl,
                (*prcm)->cm_l4per_i2c3_clkctrl,
                (*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
                (*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
                (*prcm)->cm_l3init_hsusbhost_clkctrl,
                (*prcm)->cm_l3init_fsusb_clkctrl,
                0
@@ -558,6 +581,47 @@ void enable_basic_uboot_clocks(void)
                         1);
 }
 
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+       u32 const clk_domains_edma3[] = {
+               0
+       };
+
+       u32 const clk_modules_hw_auto_edma3[] = {
+               (*prcm)->cm_l3main1_tptc1_clkctrl,
+               (*prcm)->cm_l3main1_tptc2_clkctrl,
+               0
+       };
+
+       u32 const clk_modules_explicit_en_edma3[] = {
+               0
+       };
+
+       do_enable_clocks(clk_domains_edma3,
+                        clk_modules_hw_auto_edma3,
+                        clk_modules_explicit_en_edma3,
+                        1);
+}
+
+void disable_edma3_clocks(void)
+{
+       u32 const clk_domains_edma3[] = {
+               0
+       };
+
+       u32 const clk_modules_disable_edma3[] = {
+               (*prcm)->cm_l3main1_tptc1_clkctrl,
+               (*prcm)->cm_l3main1_tptc2_clkctrl,
+               0
+       };
+
+       do_disable_clocks(clk_domains_edma3,
+                         clk_modules_disable_edma3,
+                         1);
+}
+#endif
+
 const struct ctrl_ioregs ioregs_omap5430 = {
        .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
        .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
@@ -592,8 +656,8 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddrch = 0x40404040,
        .ctrl_lpddr2ch = 0x40404040,
        .ctrl_ddr3ch = 0x80808080,
-       .ctrl_ddrio_0 = 0xA2084210,
-       .ctrl_ddrio_1 = 0x84210840,
+       .ctrl_ddrio_0 = 0x00094A40,
+       .ctrl_ddrio_1 = 0x04A52000,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
        .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -604,8 +668,8 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
        .ctrl_ddrch = 0x40404040,
        .ctrl_lpddr2ch = 0x40404040,
        .ctrl_ddr3ch = 0x60606080,
-       .ctrl_ddrio_0 = 0xA2084210,
-       .ctrl_ddrio_1 = 0x84210840,
+       .ctrl_ddrio_0 = 0x00094A40,
+       .ctrl_ddrio_1 = 0x04A52000,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
        .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
@@ -636,6 +700,7 @@ void __weak hw_data_init(void)
 
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA752_ES2_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
        *omap_vcores = &dra752_volts;
@@ -671,6 +736,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA752_ES2_0:
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0: