ARM: DRA7xx: ctrl: Fix efuse register addresses

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5c60d743c9de71725bd4eadaa5668f7878611085..ff08ef42479400a5697ba210c7b313ae9165a67c 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_phy_power_sata                 = 0x4A002374,
        .control_core_mac_id_0_lo               = 0x4A002514,
        .control_core_mac_id_0_hi               = 0x4A002518,
        .control_core_mac_id_1_lo               = 0x4A00251C,
@@ -431,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_srcomp_code_latch              = 0x4A002E84,
        .control_ddr_control_ext_0              = 0x4A002E88,
        .control_padconf_core_base              = 0x4A003400,
+       .control_std_fuse_opp_vdd_mpu_2         = 0x4A003B20,
        .control_port_emif1_sdram_config        = 0x4AE0C110,
        .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
        .control_port_emif2_sdram_config        = 0x4AE0C118,
        .control_emif1_sdram_config_ext         = 0x4AE0C144,
        .control_emif2_sdram_config_ext         = 0x4AE0C148,
+       .control_wkup_ldovbb_mpu_voltage_ctrl   = 0x4AE0C158,
        .control_padconf_mode                   = 0x4AE0C5A0,
        .control_xtal_oscillator                = 0x4AE0C5A4,
        .control_i2c_2                          = 0x4AE0C5A8,
@@ -444,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_wkup_control_spare_r           = 0x4AE0C5B4,
        .control_wkup_control_spare_r_c0        = 0x4AE0C5B8,
        .control_srcomp_east_side_wkup          = 0x4AE0C5BC,
-       .control_efuse_1                        = 0x4AE0C5C0,
-       .control_efuse_2                        = 0x4AE0C5C4,
-       .control_efuse_3                        = 0x4AE0C5C8,
-       .control_efuse_4                        = 0x4AE0C5CC,
+       .control_efuse_1                        = 0x4AE0C5C8,
+       .control_efuse_2                        = 0x4AE0C5CC,
+       .control_efuse_3                        = 0x4AE0C5D0,
+       .control_efuse_4                        = 0x4AE0C5D4,
        .control_efuse_13                       = 0x4AE0C5F0,
 };
 
@@ -806,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_dsp_clkstctrl                       = 0x4a005400,
        .cm_dsp_dsp_clkctrl                     = 0x4a005420,
 
+       /* prm irqstatus regs */
+       .prm_irqstatus_mpu_2                    = 0x4ae06014,
+
        /* cm2.ckgen */
        .cm_clksel_usb_60mhz                    = 0x4a008104,
        .cm_clkmode_dpll_per                    = 0x4a008140,
@@ -895,9 +901,11 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
        .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
        .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
+       .cm_l3init_sata_clkctrl                 = 0x4a009388,
        .cm_gmac_clkstctrl                      = 0x4a0093c0,
        .cm_gmac_gmac_clkctrl                   = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
+       .cm_l3init_ocp2scp3_clkctrl             = 0x4a0093e8,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl                     = 0x4a009700,
@@ -964,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
        .prm_vc_val_bypass                      = 0x4ae07da0,
        .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
        .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,
+
+       .prm_abbldo_mpu_setup                   = 0x4AE07DDC,
+       .prm_abbldo_mpu_ctrl                    = 0x4AE07DE0,
 };