Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index db8e9d2f189523b3c3151b890a63550c3693ebd6..d23dc9d719b926cc7f2e3b978fbc728d1df8a2e8 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -32,6 +32,7 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
+#include <asm/system.h>
 
 .globl _start
 _start: b      reset
@@ -143,29 +144,22 @@ reset:
        orr     r0, r0, #0xd3
        msr     cpsr,r0
 
-#if defined(CONFIG_OMAP34XX)
-       /* Copy vectors to mask ROM indirect addr */
-       adr     r0, _start              @ r0 <- current position of code
-       add     r0, r0, #4              @ skip reset vector
-       mov     r2, #64                 @ r2 <- size to copy
-       add     r2, r0, r2              @ r2 <- source end address
-       mov     r1, #SRAM_OFFSET0       @ build vect addr
-       mov     r3, #SRAM_OFFSET1
-       add     r1, r1, r3
-       mov     r3, #SRAM_OFFSET2
-       add     r1, r1, r3
-next:
-       ldmia   r0!, {r3 - r10}         @ copy from source address [r0]
-       stmia   r1!, {r3 - r10}         @ copy to   target address [r1]
-       cmp     r0, r2                  @ until source end address [r2]
-       bne     next                    @ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-       /* No need to copy/exec the clock code - DPLL adjust already done
-        * in NAND/oneNAND Boot.
-        */
-       bl      cpy_clk_code            @ put dpll adjust code behind vectors
-#endif /* NAND Boot */
+/*
+ * Setup vector:
+ * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
+ * Continue to use ROM code vector only in OMAP4 spl)
+ */
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+       /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
+       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
+       bic     r0, #CR_V               @ V = 0
+       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
+
+       /* Set vector address in CP15 VBAR register */
+       ldr     r0, =_start
+       mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
 #endif
+
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_crit