arm: mx6: use fuse_read() for OCOTP fuse access

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / sunxi / pinmux.c

diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 1f2843fcac4577ebcfa45212b27c9238399e7347..b026f78ca50785a198e68295496093d1ab67a06b 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/pinmux.c
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -10,32 +10,42 @@
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
-       u32 bank = GPIO_BANK(pin);
-       u32 index = GPIO_CFG_INDEX(pin);
-       u32 offset = GPIO_CFG_OFFSET(pin);
-       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+       u32 index = GPIO_CFG_INDEX(bank_offset);
+       u32 offset = GPIO_CFG_OFFSET(bank_offset);
 
        clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
-       return 0;
 }
 
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
-       u32 cfg;
        u32 bank = GPIO_BANK(pin);
-       u32 index = GPIO_CFG_INDEX(pin);
-       u32 offset = GPIO_CFG_OFFSET(pin);
        struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
+       sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+       u32 index = GPIO_CFG_INDEX(bank_offset);
+       u32 offset = GPIO_CFG_OFFSET(bank_offset);
+       u32 cfg;
+
        cfg = readl(&pio->cfg[0] + index);
        cfg >>= offset;
 
        return cfg & 0xf;
 }
 
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+       u32 bank = GPIO_BANK(pin);
+       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+       return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
 int sunxi_gpio_set_drv(u32 pin, u32 val)
 {
        u32 bank = GPIO_BANK(pin);