Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / zynq / cpu.c

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 2bb38438ae4ab6848ca80e52d62aaf40d0c0d307..7626b5c1a3b5e85a18e8560b438cf67ad1ce75b6 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -6,6 +6,7 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 
@@ -16,24 +17,26 @@ void lowlevel_init(void)
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
-       /* remap DDR to zero, FILTERSTART */
-       writel(0, &scu_base->filter_start);
-
+#ifndef CONFIG_SPL_BUILD
        /* Device config APB, unlock the PCAP */
        writel(0x757BDF0D, &devcfg_base->unlock);
        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+       /* remap DDR to zero, FILTERSTART */
+       writel(0, &scu_base->filter_start);
+
        /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
        writel(0x1F, &slcr_base->ocm_cfg);
        /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
        writel(0x0, &slcr_base->fpga_rst_ctrl);
-       /* TZ_DDR_RAM, Set DDR trust zone non-secure */
-       writel(0xFFFFFFFF, &slcr_base->trust_zone);
        /* Set urgent bits with register */
        writel(0x0, &slcr_base->ddr_urgent_sel);
        /* Urgent write, ports S2/S3 */
        writel(0xC, &slcr_base->ddr_urgent);
-
+#endif
+#endif
+       zynq_clk_early_init();
        zynq_slcr_lock();
 
        return 0;
@@ -45,3 +48,11 @@ void reset_cpu(ulong addr)
        while (1)
                ;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif