Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / zynq / cpu.c

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e75ed052fe4a6701f5c77646d067eb6c60..7626b5c1a3b5e85a18e8560b438cf67ad1ce75b6 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -6,6 +6,7 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 
@@ -16,7 +17,7 @@ void lowlevel_init(void)
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
        /* Device config APB, unlock the PCAP */
        writel(0x757BDF0D, &devcfg_base->unlock);
        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@@ -34,7 +35,8 @@ int arch_cpu_init(void)
        /* Urgent write, ports S2/S3 */
        writel(0xC, &slcr_base->ddr_urgent);
 #endif
-
+#endif
+       zynq_clk_early_init();
        zynq_slcr_lock();
 
        return 0;
@@ -46,3 +48,11 @@ void reset_cpu(ulong addr)
        while (1)
                ;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif