Arm64 fix a bug of vbar_el3 initialization

[karo-tx-uboot.git] / arch / arm / cpu / tegra-common / ap.c

diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 236cda8419fc0ce5c4444d201cee35308b35c17a..91d70da6566161f7b83715a406b660246fe40984 100644 (file)
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -1,24 +1,8 @@
 /*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
 * NVIDIA Corporation <www.nvidia.com>
 *
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
 */
 
 /* Tegra AP (Application Processor) code */
@@ -34,25 +18,45 @@
 #include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
 
-int tegra_get_chip_type(void)
+int tegra_get_chip(void)
 {
-       struct apb_misc_gp_ctlr *gp;
-       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-       uint tegra_sku_id, rev;
+       int rev;
+       struct apb_misc_gp_ctlr *gp =
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        /*
         * This is undocumented, Chip ID is bits 15:8 of the register
         * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-        * Tegra30, and 0x35 for T114.
+        * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
         */
-       gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+       debug("%s: CHIPID is 0x%02X\n", __func__, rev);
+
+       return rev;
+}
+
+int tegra_get_sku_info(void)
+{
+       int sku_id;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+
+       sku_id = readl(&fuse->sku_info) & 0xff;
+       debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
 
-       tegra_sku_id = readl(&fuse->sku_info) & 0xff;
+       return sku_id;
+}
+
+int tegra_get_chip_sku(void)
+{
+       uint sku_id, chip_id;
 
-       switch (rev) {
+       chip_id = tegra_get_chip();
+       sku_id = tegra_get_sku_info();
+
+       switch (chip_id) {
        case CHIPID_TEGRA20:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
+               case SKU_ID_T20_7:
                case SKU_ID_T20:
                        return TEGRA_SOC_T20;
                case SKU_ID_T25SE:
@@ -64,19 +68,34 @@ int tegra_get_chip_type(void)
                }
                break;
        case CHIPID_TEGRA30:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
+               case SKU_ID_T33:
                case SKU_ID_T30:
+               case SKU_ID_TM30MQS_P_A3:
+               default:
                        return TEGRA_SOC_T30;
                }
                break;
        case CHIPID_TEGRA114:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
                case SKU_ID_T114_ENG:
+               case SKU_ID_T114_1:
+               default:
                        return TEGRA_SOC_T114;
                }
                break;
+       case CHIPID_TEGRA124:
+               switch (sku_id) {
+               case SKU_ID_T124_ENG:
+               default:
+                       return TEGRA_SOC_T124;
+               }
+               break;
        }
-       /* unknown sku id */
+
+       /* unknown chip/sku id */
+       printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
+               __func__, chip_id, sku_id);
        return TEGRA_SOC_UNKNOWN;
 }
 
@@ -85,6 +104,10 @@ static void enable_scu(void)
        struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
        u32 reg;
 
+       /* Only enable the SCU on T20/T25 */
+       if (tegra_get_chip() != CHIPID_TEGRA20)
+               return;
+
        /* If SCU already setup/enabled, return */
        if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
                return;
@@ -104,8 +127,8 @@ static u32 get_odmdata(void)
         * ODMDATA is stored in the BCT in IRAM by the BootROM.
         * The BCT start and size are stored in the BIT in IRAM.
         * Read the data @ bct_start + (bct_size - 12). This works
-        * on T20 and T30 BCTs, which are locked down. If this changes
-        * in new chips (T114, etc.), we can revisit this algorithm.
+        * on BCTs for currently supported SoCs, which are locked down.
+        * If this changes in new chips, we can revisit this algorithm.
         */
 
        u32 bct_start, odmdata;
@@ -138,11 +161,6 @@ void s_init(void)
 
        enable_scu();
 
-       /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-       asm volatile(
-               "mrc    p15, 0, r0, c1, c0, 1\n"
-               "orr    r0, r0, #0x41\n"
-               "mcr    p15, 0, r0, c1, c0, 1\n");
-
-       /* FIXME: should have SoC's L2 disabled too? */
+       /* init the cache */
+       config_cache();
 }