/*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra AP (Application Processor) code */
/*
* This is undocumented, Chip ID is bits 15:8 of the register
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, and 0x35 for T114.
+ * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
debug("%s: CHIPID is 0x%02X\n", __func__, rev);
switch (sku_id) {
case SKU_ID_T33:
case SKU_ID_T30:
+ case SKU_ID_TM30MQS_P_A3:
+ default:
return TEGRA_SOC_T30;
}
break;
switch (sku_id) {
case SKU_ID_T114_ENG:
case SKU_ID_T114_1:
+ default:
return TEGRA_SOC_T114;
}
break;
+ case CHIPID_TEGRA124:
+ switch (sku_id) {
+ case SKU_ID_T124_ENG:
+ default:
+ return TEGRA_SOC_T124;
+ }
+ break;
}
+
/* unknown chip/sku id */
printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
__func__, chip_id, sku_id);
* ODMDATA is stored in the BCT in IRAM by the BootROM.
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
- * on T20 and T30 BCTs, which are locked down. If this changes
- * in new chips (T114, etc.), we can revisit this algorithm.
+ * on BCTs for currently supported SoCs, which are locked down.
+ * If this changes in new chips, we can revisit this algorithm.
*/
u32 bct_start, odmdata;