Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[karo-tx-uboot.git] / arch / arm / cpu / tegra-common / ap.c

diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 236cda8419fc0ce5c4444d201cee35308b35c17a..e099683890457797188f30bb39c820cfccc682d5 100644 (file)
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -34,25 +34,45 @@
 #include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
 
-int tegra_get_chip_type(void)
+int tegra_get_chip(void)
 {
-       struct apb_misc_gp_ctlr *gp;
-       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-       uint tegra_sku_id, rev;
+       int rev;
+       struct apb_misc_gp_ctlr *gp =
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        /*
         * This is undocumented, Chip ID is bits 15:8 of the register
         * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
         * Tegra30, and 0x35 for T114.
         */
-       gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+       debug("%s: CHIPID is 0x%02X\n", __func__, rev);
+
+       return rev;
+}
+
+int tegra_get_sku_info(void)
+{
+       int sku_id;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
-       tegra_sku_id = readl(&fuse->sku_info) & 0xff;
+       sku_id = readl(&fuse->sku_info) & 0xff;
+       debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
 
-       switch (rev) {
+       return sku_id;
+}
+
+int tegra_get_chip_sku(void)
+{
+       uint sku_id, chip_id;
+
+       chip_id = tegra_get_chip();
+       sku_id = tegra_get_sku_info();
+
+       switch (chip_id) {
        case CHIPID_TEGRA20:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
+               case SKU_ID_T20_7:
                case SKU_ID_T20:
                        return TEGRA_SOC_T20;
                case SKU_ID_T25SE:
@@ -64,19 +84,23 @@ int tegra_get_chip_type(void)
                }
                break;
        case CHIPID_TEGRA30:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
+               case SKU_ID_T33:
                case SKU_ID_T30:
                        return TEGRA_SOC_T30;
                }
                break;
        case CHIPID_TEGRA114:
-               switch (tegra_sku_id) {
+               switch (sku_id) {
                case SKU_ID_T114_ENG:
+               case SKU_ID_T114_1:
                        return TEGRA_SOC_T114;
                }
                break;
        }
-       /* unknown sku id */
+       /* unknown chip/sku id */
+       printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
+               __func__, chip_id, sku_id);
        return TEGRA_SOC_UNKNOWN;
 }
 
@@ -138,11 +162,6 @@ void s_init(void)
 
        enable_scu();
 
-       /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-       asm volatile(
-               "mrc    p15, 0, r0, c1, c0, 1\n"
-               "orr    r0, r0, #0x41\n"
-               "mcr    p15, 0, r0, c1, c0, 1\n");
-
-       /* FIXME: should have SoC's L2 disabled too? */
+       /* init the cache */
+       config_cache();
 }