/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_START_EN (0x1)
+#define VTP_CTRL_FILTER_SHIFT 1
+#define VTP_CTRL_FILTER_MASK (0x7 << VTP_CTRL_FILTER_SHIFT)
+#define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK)
+#define VTP_CTRL_START_EN (0x1 << 0)
+#define PHY_DLL_LOCK_DIFF 0x0
#ifdef CONFIG_AM43XX
#define DDR_CKE_CTRL_NORMAL 0x3
#else
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
-#define MT47H128M16RT25E_WR_DQS 0x00
-#define MT47H128M16RT25E_PHY_WRLVL 0x00
-#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B