TX6 Release 2013-04-22

[karo-tx-uboot.git] / arch / arm / include / asm / arch-am33xx / hardware.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index e620ab3548d7b47306f920243c4862ac558d2f88..8d689282ad493a59c3e6cafecdcb66f2fe2f6280 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -19,9 +19,10 @@
 #ifndef __AM33XX_HARDWARE_H
 #define __AM33XX_HARDWARE_H
 
+#include <asm/arch/omap.h>
+
 /* Module base addresses */
 #define LOW_LEVEL_SRAM_STACK           0x4030B7FC
-#define SRAM0_START                    0x402F0400
 #define UART0_BASE                     0x44E09000
 
 /* DM Timer base addresses */
@@ -34,12 +35,6 @@
 #define DM_TIMER6_BASE                 0x48048000
 #define DM_TIMER7_BASE                 0x4804A000
 
-/* GPIO Base address */
-#define GPIO0_BASE                     0x44E07000
-#define GPIO1_BASE                     0x4804C000
-#define GPIO2_BASE                     0x481AC000
-#define GPIO3_BASE                     0x481AE000
-
 /* BCH Error Location Module */
 #define ELM_BASE                       0x48080000
 
@@ -48,6 +43,7 @@
 
 /* Control Module Base Address */
 #define CTRL_BASE                      0x44E10000
+#define CTRL_DEVICE_BASE               0x44E10600
 
 /* PRCM Base Address */
 #define PRCM_BASE                      0x44E00000
@@ -55,13 +51,13 @@
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE               0x4C000000
 #define EMIF4_1_CFG_BASE               0x4D000000
-#define DMM_BASE                       0x4E000000
 
 /* PLL related registers */
 #define CM_PER                         0x44E00000
 #define CM_WKUP                                0x44E00400
 #define CM_DPLL                                0x44E00500
 #define CM_DEVICE                      0x44E00700
+#define CM_RTC                         0x44E00800
 #define CM_CEFUSE                      0x44E00A00
 #define PRM_DEVICE                     0x44E00F00
 
@@ -84,12 +80,14 @@
 #define GPMC_BASE                      0x50000000
 
 /* CPSW Config space */
-#define CPSW_BASE                      0x4A100000
-#define CPSW_MDIO_BASE                 0x4A101000
+#define AM335X_CPSW_BASE               0x4A100000
+#define AM335X_CPSW_MDIO_BASE          0x4A101000
 
 /* RTC base address */
 #define AM335X_RTC_BASE                        0x44E3E000
 
-extern unsigned long lcdc_clk_rate(void);
+/* OTG */
+#define AM335X_USB0_OTG_BASE           0x47401000
+#define AM335X_USB1_OTG_BASE           0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */