Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[karo-tx-uboot.git] / arch / arm / include / asm / arch-exynos / cpu.h

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f76e4897e9cd5196248962c09f601017fc1554bb..4b67191c07e214d25de6bcbe42ab31ff1ae0ed4e 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -2,21 +2,7 @@
  * (C) Copyright 2010 Samsung Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _EXYNOS4_CPU_H
@@ -38,9 +24,9 @@
 #define EXYNOS4_CLOCK_BASE             0x10030000
 #define EXYNOS4_SYSTIMER_BASE          0x10050000
 #define EXYNOS4_WATCHDOG_BASE          0x10060000
+#define EXYNOS4_TZPC_BASE              0x10110000
 #define EXYNOS4_MIU_BASE               0x10600000
-#define EXYNOS4_DMC0_BASE              0x10400000
-#define EXYNOS4_DMC1_BASE              0x10410000
+#define EXYNOS4_DMC_CTRL_BASE          0x10400000
 #define EXYNOS4_GPIO_PART2_BASE                0x11000000
 #define EXYNOS4_GPIO_PART1_BASE                0x11400000
 #define EXYNOS4_FIMD_BASE              0x11C00000
@@ -63,6 +49,8 @@
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_ACE_SFR_BASE           DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE           DEVICE_NOT_AVAILABLE
+#define EXYNOS4_AUDIOSS_BASE           DEVICE_NOT_AVAILABLE
 
 /* EXYNOS4X12 */
 #define EXYNOS4X12_GPIO_PART3_BASE     0x03860000
@@ -74,8 +62,8 @@
 #define EXYNOS4X12_CLOCK_BASE          0x10030000
 #define EXYNOS4X12_SYSTIMER_BASE       0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE       0x10060000
-#define EXYNOS4X12_DMC0_BASE           0x10600000
-#define EXYNOS4X12_DMC1_BASE           0x10610000
+#define EXYNOS4X12_TZPC_BASE           0x10110000
+#define EXYNOS4X12_DMC_CTRL_BASE       0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
 #define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
@@ -97,20 +85,23 @@
 #define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_ACE_SFR_BASE                DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE                DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_AUDIOSS_BASE                DEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING            0x10000
 
+#define EXYNOS5_AUDIOSS_BASE           0x03810000
 #define EXYNOS5_GPIO_PART4_BASE                0x03860000
 #define EXYNOS5_PRO_ID                 0x10000000
 #define EXYNOS5_CLOCK_BASE             0x10010000
 #define EXYNOS5_POWER_BASE             0x10040000
 #define EXYNOS5_SWRESET                        0x10040400
 #define EXYNOS5_SYSREG_BASE            0x10050000
+#define EXYNOS5_TZPC_BASE              0x10100000
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
-#define EXYNOS5_DMC_PHY0_BASE          0x10C00000
-#define EXYNOS5_DMC_PHY1_BASE          0x10C10000
+#define EXYNOS5_DMC_PHY_BASE           0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE                0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE          0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE                0x11400000
@@ -175,7 +166,7 @@ static inline char *s5p_get_cpu_name(void)
 }
 
 #define IS_SAMSUNG_TYPE(type, id)                      \
-static inline int cpu_is_##type(void)                  \
+static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
 {                                                      \
        return (s5p_cpu_id >> 12) == id;                \
 }
@@ -184,7 +175,8 @@ IS_SAMSUNG_TYPE(exynos4, 0x4)
 IS_SAMSUNG_TYPE(exynos5, 0x5)
 
 #define IS_EXYNOS_TYPE(type, id)                       \
-static inline int proid_is_##type(void)                        \
+static inline int __attribute__((no_instrument_function)) \
+       proid_is_##type(void)                           \
 {                                                      \
        return s5p_cpu_id == id;                        \
 }
@@ -194,9 +186,10 @@ IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)                             \
-static inline unsigned int samsung_get_base_##device(void)     \
+static inline unsigned int __attribute__((no_instrument_function)) \
+       samsung_get_base_##device(void) \
 {                                                              \
-       if (cpu_is_exynos4()) {                                 \
+       if (cpu_is_exynos4()) {                         \
                if (proid_is_exynos4412())                      \
                        return EXYNOS4X12_##base;               \
                return EXYNOS4_##base;                          \
@@ -233,6 +226,10 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
+SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
 #endif
 
 #endif /* _EXYNOS4_CPU_H */