keystone2: add possibility to turn off all dsps

[karo-tx-uboot.git] / arch / arm / include / asm / arch-keystone / hardware-k2hk.h

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 50ff13a3b2054eaa8643ce0f181cb8b3c78fa86d..5e2f659e9473383c736dbc3b752f96e5044f8dce 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -9,13 +9,6 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define K2HK_ASYNC_EMIF_CNTRL_BASE      0x21000a00
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   K2HK_ASYNC_EMIF_CNTRL_BASE
-#define K2HK_ASYNC_EMIF_DATA_CE0_BASE   0x30000000
-#define K2HK_ASYNC_EMIF_DATA_CE1_BASE   0x34000000
-#define K2HK_ASYNC_EMIF_DATA_CE2_BASE   0x38000000
-#define K2HK_ASYNC_EMIF_DATA_CE3_BASE   0x3c000000
-
 #define K2HK_PLL_CNTRL_BASE             0x02310000
 #define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
 #define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
@@ -23,7 +16,6 @@
 #define KS2_RSTCTRL_MASK                0xffff0000
 #define KS2_RSTCTRL_SWRST               0xfffe0000
 
-#define K2HK_PSC_BASE                   0x02350000
 #define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
 #define JTAG_ID_REG                     (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define K2HK_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
@@ -76,7 +68,6 @@
 #define K2HK_LPSC_VUSR0                12
 #define K2HK_LPSC_CHIP_SRSS            13
 #define K2HK_LPSC_MSMC                 14
-#define K2HK_LPSC_GEM_0                15
 #define K2HK_LPSC_GEM_1                16
 #define K2HK_LPSC_GEM_2                17
 #define K2HK_LPSC_GEM_3                18
@@ -113,9 +104,6 @@
 #define K2HK_LPSC_VUSR1                49
 #define K2HK_LPSC_XGE                  50
 #define K2HK_LPSC_ARM_SREFLEX          51
-#define K2HK_LPSC_TETRIS               52
-
-#define K2HK_UART0_BASE                0x02530c00
 
 /* DDR3A definitions */
 #define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
@@ -147,4 +135,7 @@
 /* MSMC control */
 #define K2HK_MSMC_CTRL_BASE             0x0bc00000
 
+/* Number of DSP cores */
+#define KS2_NUM_DSPS                   8
+
 #endif /* __ASM_ARCH_HARDWARE_H */