keystone2: add possibility to turn off all dsps

[karo-tx-uboot.git] / arch / arm / include / asm / arch-keystone / hardware.h

diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 6c532ca8700bfffad852e90ea1eaf7064ffb1165..0dcc31a64592f13519cd5aadac2a419ed96ec015 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,68 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-#define ASYNC_EMIF_NUM_CS               4
-#define ASYNC_EMIF_MODE_NOR             0
-#define ASYNC_EMIF_MODE_NAND            1
-#define ASYNC_EMIF_MODE_ONENAND         2
-#define ASYNC_EMIF_PRESERVE             -1
-
-struct async_emif_config {
-       unsigned mode;
-       unsigned select_strobe;
-       unsigned extend_wait;
-       unsigned wr_setup;
-       unsigned wr_strobe;
-       unsigned wr_hold;
-       unsigned rd_setup;
-       unsigned rd_strobe;
-       unsigned rd_hold;
-       unsigned turn_around;
-       enum {
-               ASYNC_EMIF_8    = 0,
-               ASYNC_EMIF_16   = 1,
-               ASYNC_EMIF_32   = 2,
-       } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-struct ddr3_phy_config {
-       unsigned int pllcr;
-       unsigned int pgcr1_mask;
-       unsigned int pgcr1_val;
-       unsigned int ptr0;
-       unsigned int ptr1;
-       unsigned int ptr2;
-       unsigned int ptr3;
-       unsigned int ptr4;
-       unsigned int dcr_mask;
-       unsigned int dcr_val;
-       unsigned int dtpr0;
-       unsigned int dtpr1;
-       unsigned int dtpr2;
-       unsigned int mr0;
-       unsigned int mr1;
-       unsigned int mr2;
-       unsigned int dtcr;
-       unsigned int pgcr2;
-       unsigned int zq0cr1;
-       unsigned int zq1cr1;
-       unsigned int zq2cr1;
-       unsigned int pir_v1;
-       unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
-       unsigned int sdcfg;
-       unsigned int sdtim1;
-       unsigned int sdtim2;
-       unsigned int sdtim3;
-       unsigned int sdtim4;
-       unsigned int zqcfg;
-       unsigned int sdrfc;
-};
-
 #endif
 
 #define                BIT(x)  (1 << (x))
@@ -142,9 +80,24 @@ struct ddr3_emif_config {
 #define KS2_DDR3_PMCTL_OFFSET           0x38
 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
 
+#define KS2_DDR3_PLLCTRL_PHY_RESET     0x80000000
+
 #define KS2_UART0_BASE                 0x02530c00
 #define KS2_UART1_BASE                 0x02531000
 
+/* PSC */
+#define KS2_PSC_BASE                   0x02350000
+#define KS2_LPSC_GEM_0                 15
+#define KS2_LPSC_TETRIS                        52
+#define KS2_TETRIS_PWR_DOMAIN          31
+
+/* AEMIF */
+#define KS2_AEMIF_CNTRL_BASE           0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
+
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON              0x1
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
@@ -168,9 +121,6 @@ static inline int cpu_revision(void)
 
 void share_all_segments(int priv_id);
 int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
 void sdelay(unsigned long);
 
 #endif