#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
+
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
/* PSC */
#define KS2_PSC_BASE 0x02350000
+#define KS2_LPSC_GEM_0 15
+#define KS2_LPSC_TETRIS 52
+#define KS2_TETRIS_PWR_DOMAIN 31
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON 0x1
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif