u32 sdhcpcr;
};
-#define SCFG_SCFGREVCR_REV 0xffffffff
-#define SCFG_SCFGREVCR_NOREV 0
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
/* CCI-400 registers */
struct ccsr_cci400 {