imx: Make imx25 compatible to mxc_gpio driver and fix in tx25

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx25 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index f5a2929e2209bf522fe156328232d67329393a23..2ccb445975950c21b1ff6c565dc81208b53c20c4 100644 (file)
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -36,6 +36,7 @@
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_FEC_MXC
 extern void mx25_fec_init_pins(void);
+extern void imx_get_mac_from_fuse(unsigned char *mac);
 #endif
 
 /* Clock Control Module (CCM) registers */
@@ -85,8 +86,8 @@ struct esdramc_regs {
 
 /* GPIO registers */
 struct gpio_regs {
-       u32 dr;         /* data */
-       u32 dir;        /* direction */
+       u32 gpio_dr;    /* data */
+       u32 gpio_dir;   /* direction */
        u32 psr;        /* pad satus */
        u32 icr1;       /* interrupt config 1 */
        u32 icr2;       /* interrupt config 2 */
@@ -129,12 +130,56 @@ struct iim_regs {
        u32 iim_srev;
        u32 iim_prog_p;
        u32 res1[0x1f5];
-       u32 iim_bank_area0[0x20];
-       u32 res2[0xe0];
-       u32 iim_bank_area1[0x20];
-       u32 res3[0xe0];
-       u32 iim_bank_area2[0x20];
+       struct fuse_bank {
+               u32 fuse_regs[0x20];
+               u32 fuse_rsvd[0xe0];
+       } bank[3];
 };
+
+struct fuse_bank0_regs {
+       u32 fuse0_25[0x1a];
+       u32 mac_addr[6];
+};
+
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+       u32 mpr0;
+       u32 pad00[3];
+       u32 sgpcr0;
+       u32 pad01[59];
+       u32 mpr1;
+       u32 pad02[3];
+       u32 sgpcr1;
+       u32 pad03[59];
+       u32 mpr2;
+       u32 pad04[3];
+       u32 sgpcr2;
+       u32 pad05[59];
+       u32 mpr3;
+       u32 pad06[3];
+       u32 sgpcr3;
+       u32 pad07[59];
+       u32 mpr4;
+       u32 pad08[3];
+       u32 sgpcr4;
+       u32 pad09[251];
+       u32 mgpcr0;
+       u32 pad10[63];
+       u32 mgpcr1;
+       u32 pad11[63];
+       u32 mgpcr2;
+       u32 pad12[63];
+       u32 mgpcr3;
+       u32 pad13[63];
+       u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+       u32 mpr_0_7;
+       u32 mpr_8_15;
+};
+
 #endif
 
 /* AIPS 1 */
@@ -312,7 +357,10 @@ struct iim_regs {
 #define WSR_UNLOCK1            0x5555
 #define WSR_UNLOCK2            0xAAAA
 
-/* FUSE bank offsets */
-#define IIM0_MAC               0x1a
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR                IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR                IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR                IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR                IMX_GPIO4_BASE
 
 #endif                         /* _IMX_REGS_H */