#include <asm/imx-common/iomux-v3.h>
/* Pad control groupings */
-#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+#define MX51_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)
-#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+#define MX51_ESDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)
-#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+#define MX51_USBH_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
-#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
+#define MX51_ECSPI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS | \
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
+#define MX51_SDHCI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
PAD_CTL_SRE_FAST | PAD_CTL_DVS)
-#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+#define MX51_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+#define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+#define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_3 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A21__BOOT_UART_SRC1 = IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A21__EIM_A21 = IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A21__GPIO2_15 = IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__CSI1_D7 = IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__DISP1_EXT_CLK = IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__EIM_CS5 = IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__GPIO2_30 = IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__USBOTG_DIR = IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__NANDF_CS2 = IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__GPIO3_18 = IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__SD4_CLK = IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+ MX51_PAD_NANDF_CS2__CSPI_SCLK = IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__USBH3_H1_DP = IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_VSYNC__CSI2_VSYNC = IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_VSYNC__GPIO4_13 = IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_HSYNC__CSI2_HSYNC = IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_HSYNC__GPIO4_14 = IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_I2C1_CLK__GPIO4_16 = IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_I2C1_DAT__GPIO4_17 = IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL),
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS = IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 = IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 = IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0 = IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1 = IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2 = IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3 = IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4 = IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5 = IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT6__BOOT_USB_SRC = IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6 = IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG = IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7 = IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT8__BOOT_SRC0 = IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8 = IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT9__BOOT_SRC1 = IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9 = IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE = IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10 = IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 = IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11 = IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL = IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12 = IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 = IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13 = IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 = IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14 = IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH = IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15 = IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 = IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16 = IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 = IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17 = IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 = IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18 = IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT18__DISP2_PIN11 = IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT18__DISP2_PIN5 = IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 = IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19 = IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT19__DISP2_PIN12 = IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT19__DISP2_PIN6 = IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 = IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20 = IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT20__DISP2_PIN13 = IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT20__DISP2_PIN7 = IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 = IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21 = IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT21__DISP2_PIN14 = IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT21__DISP2_PIN8 = IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 = IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22 = IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT22__DISP2_D0_CS = IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT22__DISP2_DAT16 = IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 = IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23 = IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT23__DISP2_D1_CS = IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT23__DISP2_DAT17 = IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DISP1_DAT23__DISP2_SER_CS = IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_1__CSPI_MISO = IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL),
MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_4__DISP2_EXT_CLK = IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_4__EIM_RDY = IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_4__WDOG1_WDOG_B = IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_8__CSI2_DATA_EN = IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_8__GPIO1_8 = IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_9__CCM_OUT_1 = IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_9__DISP2_D1_CS = IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_9__DISP2_SER_CS = IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_9__GPIO1_9 = IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_9__SD2_LCTL = IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_9__USBH3_OC = IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO1_8__USBH3_PWR = IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL),
MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
projects / karo-tx-uboot.git / blobdiff