u32 CCGR6; /* 0x0080 */
u32 CCGR7;
u32 cmeor;
- u32 resv[0xfdd];
- u32 analog_pll_sys; /* 0x4000 */
- u32 analog_pll_sys_set;
- u32 analog_pll_sys_clr;
- u32 analog_pll_sys_tog;
- u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
- u32 analog_usb1_pll_480_ctrl_set;
- u32 analog_usb1_pll_480_ctrl_clr;
- u32 analog_usb1_pll_480_ctrl_tog;
- u32 analog_reserved0[4];
- u32 analog_pll_528; /* 0x4030 */
- u32 analog_pll_528_set;
- u32 analog_pll_528_clr;
- u32 analog_pll_528_tog;
- u32 analog_pll_528_ss; /* 0x4040 */
- u32 analog_reserved1[3];
- u32 analog_pll_528_num; /* 0x4050 */
- u32 analog_reserved2[3];
- u32 analog_pll_528_denom; /* 0x4060 */
- u32 analog_reserved3[3];
- u32 analog_pll_audio; /* 0x4070 */
- u32 analog_pll_audio_set;
- u32 analog_pll_audio_clr;
- u32 analog_pll_audio_tog;
- u32 analog_pll_audio_num; /* 0x4080*/
- u32 analog_reserved4[3];
- u32 analog_pll_audio_denom; /* 0x4090 */
- u32 analog_reserved5[3];
- u32 analog_pll_video; /* 0x40a0 */
- u32 analog_pll_video_set;
- u32 analog_pll_video_clr;
- u32 analog_pll_video_tog;
- u32 analog_pll_video_num; /* 0x40b0 */
- u32 analog_reserved6[3];
- u32 analog_pll_video_denom; /* 0x40c0 */
- u32 analog_reserved7[7];
- u32 analog_pll_enet; /* 0x40e0 */
- u32 analog_pll_enet_set;
- u32 analog_pll_enet_clr;
- u32 analog_pll_enet_tog;
- u32 analog_pfd_480; /* 0x40f0 */
- u32 analog_pfd_480_set;
- u32 analog_pfd_480_clr;
- u32 analog_pfd_480_tog;
- u32 analog_pfd_528; /* 0x4100 */
- u32 analog_pfd_528_set;
- u32 analog_pfd_528_clr;
- u32 analog_pfd_528_tog;
};
#endif
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
-#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
-#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
+#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
#ifdef CONFIG_MX6SX
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
-#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
#ifndef CONFIG_MX6SX
-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
#endif
-#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
#ifndef CONFIG_MX6SX
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
#endif
-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
#ifndef CONFIG_MX6SX
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
#endif
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
#ifndef CONFIG_MX6SX
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
#endif
/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
#else
-#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
#endif
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
/* Define the bits in register CSCMR2 */
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
#endif
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
-#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
#endif
/* Define the bits in register CSCDR1 */
#ifndef CONFIG_MX6SX
-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
#endif
-#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
-#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
-#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
-#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
#ifndef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
#endif
#ifdef CONFIG_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
-#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
#else
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
#endif
#endif
+#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
-#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
-#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
-#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
-#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
-#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
#else
-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#endif
-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
/* Define the bits in register CDCDR */
#ifndef CONFIG_MX6SX
-#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
-#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
#endif
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
/* Define the bits in register CHSCCDR */
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
-#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
-#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
-#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
-#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
-#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
#else
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
#endif
-#define CHSCCDR_CLK_SEL_LDB_DI0 3
-#define CHSCCDR_PODF_DIVIDE_BY_3 2
-#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
-
/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
/* All IPU2_DI1 are LCDIF1 on MX6SX */
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
/* All IPU2_DI0 are LCDIF2 on MX6SX */
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
#endif
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
#ifndef CONFIG_MX6SX
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
#endif
-#define MXC_CCM_CLPCR_LPM_MASK 0x3
+#define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
#define MXC_CCM_CLPCR_LPM_OFFSET 0
/* Define the bits in register CISR */
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
#define MXC_CCM_CISR_COSC_READY (1 << 6)
-#define MXC_CCM_CISR_LRF_PLL 1
+#define MXC_CCM_CISR_LRF_PLL (1 << 0)
/* Define the bits in register CIMR */
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
-#define MXC_CCM_CIMR_MASK_LRF_PLL 1
+#define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
/* Define the bits in registers CGPR */
#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
-#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
#endif
-#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
-#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
-#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
-#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
-#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
-#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
-#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
-#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
-#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+#define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+#define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+#define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+#define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+#define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+#define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
+#define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ARM_DIV_SELECT 0
+#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
+#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+ BM_ANADIG_PLL_ARM_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_528_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_528_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_528_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_528_CTRL_POWER (1 << 12)
+#define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_528_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_528_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_PLL_528_CTRL_CONTROL0 2
+#define BM_ANADIG_PLL_528_CTRL_CONTROL0 (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
+#define BF_ANADIG_PLL_528_CTRL_CONTROL0(v) \
+ (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) & \
+ BM_ANADIG_PLL_528_CTRL_CONTROL0)
+#define BP_ANADIG_PLL_528_CTRL_DIV_SELECT 0
+#define BM_ANADIG_PLL_528_CTRL_DIV_SELECT (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
+#define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) & \
+ BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
+ BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
+ BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
+ BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
+ BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
+ BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
+ (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
+ BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
+#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
+ BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
+ BM_ANADIG_PFD_480_PFD3_FRAC)
+
+#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
+#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
+ BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
+#define BP_ANADIG_ANA_MISC0_ANAMUX 21
+#define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
+#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
+ BM_ANADIG_ANA_MISC0_ANAMUX)
+#define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
+#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
+#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
+ BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
+#define BP_ANADIG_ANA_MISC0_OSC_I 14
+#define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
+#define BF_ANADIG_ANA_MISC0_OSC_I(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
+ BM_ANADIG_ANA_MISC0_OSC_I)
+#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
+#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
+#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
+ BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
+#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
+ BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
+#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
+
+#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
+#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
+#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
+#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
+ (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
+ BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
+#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
+ (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
+ BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+
+#define BP_ANADIG_ANA_MISC2_CONTROL3 30
+#define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
+#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
+ BM_ANADIG_ANA_MISC2_CONTROL3)
+#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
+#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
+#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
+#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
+ BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
+#define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
+#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
+#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
+#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
+#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
+#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
+#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
+#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
+#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
+#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
+#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
+#define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
+#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
+#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
+#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
+#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
+ BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+
+#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
+#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
+ BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
+#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
+ BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
+#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
+#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
+#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
+ BM_ANADIG_TEMPSENSE0_VBGADJ)
+#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
+#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
+#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
+
+#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
+#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
+ BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
#ifdef CONFIG_MX6SX
-#define MXC_CCM_CCGR6_PWM8_OFFSET 16
-#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
-#define MXC_CCM_CCGR6_VADC_OFFSET 20
-#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
-#define MXC_CCM_CCGR6_GIS_OFFSET 22
-#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
-#define MXC_CCM_CCGR6_I2C4_OFFSET 24
-#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
-#define MXC_CCM_CCGR6_PWM5_OFFSET 26
-#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
-#define MXC_CCM_CCGR6_PWM6_OFFSET 28
-#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
-#define MXC_CCM_CCGR6_PWM7_OFFSET 30
-#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
+#define MXC_CCM_CCGR6_PWM8_OFFSET 16
+#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
+#define MXC_CCM_CCGR6_VADC_OFFSET 20
+#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
+#define MXC_CCM_CCGR6_GIS_OFFSET 22
+#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
+#define MXC_CCM_CCGR6_I2C4_OFFSET 24
+#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
+#define MXC_CCM_CCGR6_PWM5_OFFSET 26
+#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
+#define MXC_CCM_CCGR6_PWM6_OFFSET 28
+#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
+#define MXC_CCM_CCGR6_PWM7_OFFSET 30
+#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
#else
-#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
#endif
-#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
-#define BP_ANADIG_PLL_SYS_RSVD0 20
-#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
-#define BF_ANADIG_PLL_SYS_RSVD0(v) \
- (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
-#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
-#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
-#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
-#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-
-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
-#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
-#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
- (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
- (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_PLL_528_LOCK 0x80000000
-#define BP_ANADIG_PLL_528_RSVD1 19
-#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
-#define BF_ANADIG_PLL_528_RSVD1(v) \
- (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_528_BYPASS 0x00010000
-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_528_ENABLE 0x00002000
-#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_528_RSVD0 1
-#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
-#define BF_ANADIG_PLL_528_RSVD0(v) \
- (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
-#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
-
-#define BP_ANADIG_PLL_528_SS_STOP 16
-#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
-#define BF_ANADIG_PLL_528_SS_STOP(v) \
- (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
-#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
-#define BP_ANADIG_PLL_528_SS_STEP 0
-#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
-#define BF_ANADIG_PLL_528_SS_STEP(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
-
-#define BP_ANADIG_PLL_528_NUM_RSVD0 30
-#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
-#define BP_ANADIG_PLL_528_NUM_A 0
-#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
-
-#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
-#define BP_ANADIG_PLL_528_DENOM_B 0
-#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
-
-#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
-#define BP_ANADIG_PLL_AUDIO_RSVD0 22
-#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
-#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
-#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
-#define BP_ANADIG_PLL_AUDIO_NUM_A 0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
-
-#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
-#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-
-#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
-#define BP_ANADIG_PLL_VIDEO_RSVD0 22
-#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
-#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
-#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
-#define BP_ANADIG_PLL_VIDEO_NUM_A 0
-#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
-
-#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
-#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-
-#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
-#define BP_ANADIG_PLL_ENET_RSVD1 21
-#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
-#define BF_ANADIG_PLL_ENET_RSVD1(v) \
- (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
-#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
-#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_ENET_RSVD0 2
-#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
-#define BF_ANADIG_PLL_ENET_RSVD0(v) \
- (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
-#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_480_PFD3_FRAC 24
-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
-#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_480_PFD2_FRAC 16
-#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
-#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_480_PFD1_FRAC 8
-#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
-#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_480_PFD0_FRAC 0
-#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
-
-#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
-#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_528_PFD3_FRAC 24
-#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
-#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
-#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_528_PFD2_FRAC 16
-#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
-#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_528_PFD1_FRAC 8
-#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
-#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_528_PFD0_FRAC 0
-#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+#define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
+ BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
+ BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
+#define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
+ BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK (1 << 31)
+#define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_528_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_528_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_528_DIV_SELECT 0
+#define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
+#define BF_ANADIG_PLL_528_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
+ BM_ANADIG_PLL_528_DIV_SELECT)
+
+#define BP_ANADIG_PLL_528_SS_STOP 16
+#define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+ (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
+ BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
+#define BP_ANADIG_PLL_528_SS_STEP 0
+#define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
+#define BF_ANADIG_PLL_528_SS_STEP(v) \
+ (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
+ BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_A 0
+#define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
+#define BF_ANADIG_PLL_528_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_528_NUM_A) & \
+ BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_B 0
+#define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
+#define BF_ANADIG_PLL_528_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
+ BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
+ BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
+ BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
+ BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
+ BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
+ BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
+ BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
+ BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
+ BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
+#define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
+#define BP_ANADIG_PFD_480_PFD2_FRAC 16
+#define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
+ BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
+#define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
+#define BP_ANADIG_PFD_480_PFD1_FRAC 8
+#define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
+ BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
+#define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
+#define BP_ANADIG_PFD_480_PFD0_FRAC 0
+#define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
+ BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_528_PFD3_FRAC 24
+#define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
+ BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
+#define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
+#define BP_ANADIG_PFD_528_PFD2_FRAC 16
+#define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
+ BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
+#define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
+#define BP_ANADIG_PFD_528_PFD1_FRAC 8
+#define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
+ BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
+#define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
+#define BP_ANADIG_PFD_528_PFD0_FRAC 0
+#define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
+ BM_ANADIG_PFD_528_PFD0_FRAC)
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
projects / karo-tx-uboot.git / blobdiff