config: rename CONFIG_MX* to CONFIG_SOC_MX*

[karo-tx-uboot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7368572cbc9f2b8116a2f9d0398b6d63e48dc26b..bc1c58a7b1ba5bbfbaf80cf063f9cd9c8ff85bc2 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -16,12 +16,12 @@
 #define ROMCP_ARB_BASE_ADDR            0x00000000
 #define ROMCP_ARB_END_ADDR             0x000FFFFF
 
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define GPU_2D_ARB_BASE_ADDR           0x02200000
 #define GPU_2D_ARB_END_ADDR            0x02203FFF
 #define OPENVG_ARB_BASE_ADDR           0x02204000
 #define OPENVG_ARB_END_ADDR            0x02207FFF
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)
 #define CAAM_ARB_BASE_ADDR             0x00100000
 #define CAAM_ARB_END_ADDR              0x00107FFF
 #define GPU_ARB_BASE_ADDR              0x01800000
@@ -47,20 +47,20 @@
 #define GPU_2D_ARB_END_ADDR            0x00137FFF
 #define DTCP_ARB_BASE_ADDR             0x00138000
 #define DTCP_ARB_END_ADDR              0x0013BFFF
-#endif /* CONFIG_MX6SL */
+#endif /* CONFIG_SOC_MX6SL */
 
 #define MXS_APBH_BASE                  APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE                  (APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 #define GPV2_BASE_ADDR                 0x00D00000
 #else
 #define GPV2_BASE_ADDR                 0x00200000
 #endif
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define GPV3_BASE_ADDR                 0x00E00000
 #define GPV4_BASE_ADDR                 0x00F00000
 #define GPV5_BASE_ADDR                 0x01000000
@@ -89,7 +89,7 @@
 #define AIPS1_ARB_END_ADDR             0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR            0x02100000
 #define AIPS2_ARB_END_ADDR             0x021FFFFF
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define AIPS3_BASE_ADDR                        0x02200000
 #define AIPS3_END_ADDR                 0x022FFFFF
 #define WEIM_ARB_BASE_ADDR             0x50000000
@@ -113,7 +113,7 @@
 #define WEIM_ARB_END_ADDR              0x0FFFFFFF
 #endif
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 #define MMDC0_ARB_BASE_ADDR            0x80000000
 #define MMDC0_ARB_END_ADDR             0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR            0xC0000000
@@ -125,7 +125,7 @@
 #define MMDC1_ARB_END_ADDR             0xFFFFFFFF
 #endif
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define IPU_SOC_BASE_ADDR              IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET                 0x00200000
 #endif
@@ -141,7 +141,7 @@
 #define ECSPI2_BASE_ADDR           (ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR           (ATZ1_BASE_ADDR + 0x10000)
 #define ECSPI4_BASE_ADDR           (ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define UART5_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x18000)
 #define UART1_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x20000)
 #define UART2_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x24000)
@@ -151,7 +151,7 @@
 #define UART3_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x34000)
 #define UART4_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x38000)
 #else
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define ECSPI5_BASE_ADDR           (ATZ1_BASE_ADDR + 0x18000)
 #endif
 #define UART1_BASE                 (ATZ1_BASE_ADDR + 0x20000)
@@ -162,7 +162,7 @@
 #define ASRC_BASE_ADDR             (ATZ1_BASE_ADDR + 0x34000)
 #endif
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define SPBA_BASE_ADDR             (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR              (ATZ1_BASE_ADDR + 0x40000)
 #endif
@@ -196,11 +196,11 @@
 #define SRC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x58000)
 #define GPC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x60000)
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define CSI_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR                    (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
@@ -221,7 +221,7 @@
 #define USB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x8000)
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define MSHC_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0xC000)
@@ -236,9 +236,9 @@
 #define I2C3_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x30000)
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL
 #define RNGB_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x34000)
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)
 #define ENET2_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x34000)
 #else
 #define MMDC_P1_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
@@ -249,19 +249,19 @@
 #define CSU_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x40000)
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define SAI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x54000)
 #else
 #define IP2APB_TZASC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x54000)
 #endif
 #define AUDMUX_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define SAI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x64000)
@@ -277,7 +277,7 @@
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 #define GIS_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x04000)
 #define DCIC1_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x0C000)
 #define DCIC2_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x10000)
@@ -308,7 +308,7 @@
 #define CHIP_REV_1_0                0x10
 #define CHIP_REV_1_2                0x12
 #define CHIP_REV_1_5                0x15
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 #define IRAM_SIZE                   0x00040000
 #else
 #define IRAM_SIZE                   0x00020000
@@ -445,7 +445,7 @@ struct src {
 
 
 struct iomuxc {
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
        u32 reserved[0x1000];
 #endif
        u32 gpr[14];
@@ -571,7 +571,7 @@ struct cspi_regs {
 #define MXC_CSPICON_POL                4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL      12 /* SS polarity */
 #define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL)
 #define MXC_SPI_BASE_ADDRESSES \
        ECSPI1_BASE_ADDR, \
        ECSPI2_BASE_ADDR, \
@@ -621,7 +621,7 @@ struct fuse_bank0_regs {
        reg_32(cfg6);
 };
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 struct fuse_bank4_regs {
        u32 sjc_resp_low;
        u32 rsvd0[3];