#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define L2_PL310_BASE 0x00A02000
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define PCIE_ARB_BASE_ADDR 0x01000000
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
#define IRAM_SIZE 0x00040000
#define FEC_QUIRK_ENET_MAC
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
-#ifdef CONFIG_MX6SL
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
u16 wmcr; /* Miscellaneous Control */
};
-struct gpc_regs {
- u32 ctrl; /* 0x000 */
- u32 pgr; /* 0x004 */
- u32 imr1; /* 0x008 */
- u32 imr2; /* 0x00c */
- u32 imr3; /* 0x010 */
- u32 imr4; /* 0x014 */
- u32 isr1; /* 0x018 */
- u32 isr2; /* 0x01c */
- u32 isr3; /* 0x020 */
- u32 isr4; /* 0x024 */
- u32 reserved1[0x86];
- u32 gpu_ctrl; /* 0x260 */
- u32 gpu_pupscr; /* 0x264 */
- u32 gpu_pdnscr; /* 0x268 */
- u32 gpu_sr; /* 0x26c */
- u32 reserved2[0xc];
- u32 cpu_ctrl; /* 0x2a0 */
- u32 cpu_pupscr; /* 0x2a4 */
- u32 cpu_pdnscr; /* 0x2a8 */
- u32 cpu_sr; /* 0x2ac */
-};
-
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */