* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)
struct mxs_ssp_regs {
- mxs_reg_32(hw_ssp_ctrl0)
- mxs_reg_32(hw_ssp_cmd0)
- mxs_reg_32(hw_ssp_cmd1)
- mxs_reg_32(hw_ssp_compref)
- mxs_reg_32(hw_ssp_compmask)
- mxs_reg_32(hw_ssp_timing)
- mxs_reg_32(hw_ssp_ctrl1)
- mxs_reg_32(hw_ssp_data)
- mxs_reg_32(hw_ssp_sdresp0)
- mxs_reg_32(hw_ssp_sdresp1)
- mxs_reg_32(hw_ssp_sdresp2)
- mxs_reg_32(hw_ssp_sdresp3)
- mxs_reg_32(hw_ssp_status)
-
- uint32_t reserved1[12];
-
- mxs_reg_32(hw_ssp_debug)
- mxs_reg_32(hw_ssp_version)
+ mxs_reg_32(hw_ssp_ctrl0);
+ mxs_reg_32(hw_ssp_cmd0);
+ mxs_reg_32(hw_ssp_cmd1);
+ mxs_reg_32(hw_ssp_compref);
+ mxs_reg_32(hw_ssp_compmask);
+ mxs_reg_32(hw_ssp_timing);
+ mxs_reg_32(hw_ssp_ctrl1);
+ mxs_reg_32(hw_ssp_data);
+ mxs_reg_32(hw_ssp_sdresp0);
+ mxs_reg_32(hw_ssp_sdresp1);
+ mxs_reg_32(hw_ssp_sdresp2);
+ mxs_reg_32(hw_ssp_sdresp3);
+ mxs_reg_32(hw_ssp_status);
+ reg_32(reserved[3]);
+ mxs_reg_32(hw_ssp_debug);
+ mxs_reg_32(hw_ssp_version);
};
-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)
struct mxs_ssp_regs {
- mxs_reg_32(hw_ssp_ctrl0)
- mxs_reg_32(hw_ssp_cmd0)
- mxs_reg_32(hw_ssp_cmd1)
- mxs_reg_32(hw_ssp_xfer_size)
- mxs_reg_32(hw_ssp_block_size)
- mxs_reg_32(hw_ssp_compref)
- mxs_reg_32(hw_ssp_compmask)
- mxs_reg_32(hw_ssp_timing)
- mxs_reg_32(hw_ssp_ctrl1)
- mxs_reg_32(hw_ssp_data)
- mxs_reg_32(hw_ssp_sdresp0)
- mxs_reg_32(hw_ssp_sdresp1)
- mxs_reg_32(hw_ssp_sdresp2)
- mxs_reg_32(hw_ssp_sdresp3)
- mxs_reg_32(hw_ssp_ddr_ctrl)
- mxs_reg_32(hw_ssp_dll_ctrl)
- mxs_reg_32(hw_ssp_status)
- mxs_reg_32(hw_ssp_dll_sts)
- mxs_reg_32(hw_ssp_debug)
- mxs_reg_32(hw_ssp_version)
+ mxs_reg_32(hw_ssp_ctrl0);
+ mxs_reg_32(hw_ssp_cmd0);
+ mxs_reg_32(hw_ssp_cmd1);
+ mxs_reg_32(hw_ssp_xfer_size);
+ mxs_reg_32(hw_ssp_block_size);
+ mxs_reg_32(hw_ssp_compref);
+ mxs_reg_32(hw_ssp_compmask);
+ mxs_reg_32(hw_ssp_timing);
+ mxs_reg_32(hw_ssp_ctrl1);
+ mxs_reg_32(hw_ssp_data);
+ mxs_reg_32(hw_ssp_sdresp0);
+ mxs_reg_32(hw_ssp_sdresp1);
+ mxs_reg_32(hw_ssp_sdresp2);
+ mxs_reg_32(hw_ssp_sdresp3);
+ mxs_reg_32(hw_ssp_ddr_ctrl);
+ mxs_reg_32(hw_ssp_dll_ctrl);
+ mxs_reg_32(hw_ssp_status);
+ mxs_reg_32(hw_ssp_dll_sts);
+ mxs_reg_32(hw_ssp_debug);
+ mxs_reg_32(hw_ssp_version);
};
#endif
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_SOC_MX23)
+ const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_SOC_MX28)
+ const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+ if (bus >= mxs_ssp_chan_count)
+ return 0;
+
+ if (bus < 0)
+ return 0;
+
+ return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_SOC_MX23)
+ return 0;
+#elif defined(CONFIG_SOC_MX28)
+ return clock;
+#endif
+}
+
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
{
switch (port) {
return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
case 1:
return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28
case 2:
return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
case 3:
#define SSP_CTRL0_GET_RESP (1 << 17)
#define SSP_CTRL0_ENABLE (1 << 16)
-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23
#define SSP_CTRL0_XFER_COUNT_OFFSET 0
#define SSP_CTRL0_XFER_COUNT_MASK 0xffff
#endif
#define SSP_CMD0_SLOW_CLKING_EN (1 << 22)
#define SSP_CMD0_CONT_CLKING_EN (1 << 21)
#define SSP_CMD0_APPEND_8CYC (1 << 20)
-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)
#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16)
#define SSP_CMD0_BLOCK_SIZE_OFFSET 16
#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8)
#define SSP_CMD1_CMD_ARG_MASK 0xffffffff
#define SSP_CMD1_CMD_ARG_OFFSET 0
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)
#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff
#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0
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