mtd: nand: omap: remove redundant platform specific header: arch-xx/omap_gpmc.h

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap3 / omap3.h

diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 12815f694f42bc828f6253fc964b1d58544b8b12..194b93bf56dcedd2e71ae63d5a4986b80b769afd 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -4,23 +4,7 @@
  * Richard Woodruff <r-woodruff2@ti.com>
  * Syed Mohammed Khasim <x0khasim@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _OMAP3_H_
@@ -47,13 +31,31 @@
 #define OMAP34XX_L4_PER                        0x49000000
 #define OMAP34XX_L4_IO_BASE            OMAP34XX_CORE_L4_IO_BASE
 
+/* DMA4/SDMA */
+#define OMAP34XX_DMA4_BASE              0x48056000
+
 /* CONTROL */
 #define OMAP34XX_CTRL_BASE             (OMAP34XX_L4_IO_BASE + 0x2000)
 
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+       unsigned char res[0x408];
+       unsigned int io2;               /* 0x408 */
+       unsigned char res2[0x38];
+       unsigned int io0;               /* 0x444 */
+       unsigned int io1;               /* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX            0x00000001
+
 /* UART */
 #define OMAP34XX_UART1                 (OMAP34XX_L4_IO_BASE + 0x6a000)
 #define OMAP34XX_UART2                 (OMAP34XX_L4_IO_BASE + 0x6c000)
 #define OMAP34XX_UART3                 (OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4                 (OMAP34XX_L4_PER + 0x42000)
 
 /* General Purpose Timers */
 #define OMAP34XX_GPT1                  0x48318000
@@ -86,14 +88,6 @@ struct s32ktimer {
 
 #endif /* __ASSEMBLY__ */
 
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE            0x48310000
-#define OMAP34XX_GPIO2_BASE            0x49050000
-#define OMAP34XX_GPIO3_BASE            0x49052000
-#define OMAP34XX_GPIO4_BASE            0x49054000
-#define OMAP34XX_GPIO5_BASE            0x49056000
-#define OMAP34XX_GPIO6_BASE            0x49058000
-
 #ifndef __ASSEMBLY__
 struct gpio {
        unsigned char res1[0x34];
@@ -144,9 +138,16 @@ struct gpio {
 #define SRAM_OFFSET2                   0x0000F800
 #define SRAM_VECT_CODE                 (SRAM_OFFSET0 | SRAM_OFFSET1 | \
                                         SRAM_OFFSET2)
+#define SRAM_CLK_CODE                  (SRAM_VECT_CODE + 64)
+
+#define NON_SECURE_SRAM_START          0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END            0x40210000
 
 #define LOW_LEVEL_SRAM_STACK           0x4020FFFC
 
+/* scratch area - accessible on both EMU and GP */
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
+
 #define DEBUG_LED1                     149     /* gpio */
 #define DEBUG_LED2                     150     /* gpio */
 
@@ -176,11 +177,72 @@ struct gpio {
 #define CPU_3XX_ES21           2
 #define CPU_3XX_ES30           3
 #define CPU_3XX_ES31           4
-#define CPU_3XX_MAX_REV                (CPU_3XX_ES31 + 1)
+#define CPU_3XX_ES312          7
+#define CPU_3XX_MAX_REV                8
+
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10          0
+#define CPU_37XX_ES11          1
+#define CPU_37XX_ES12          2
+#define CPU_37XX_MAX_REV       3
 
 #define CPU_3XX_ID_SHIFT       28
 
 #define WIDTH_8BIT             0x0000
 #define WIDTH_16BIT            0x1000  /* bit pos for 16 bit in gpmc */
 
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX       0xb7ae
+#define HAWKEYE_AM35XX         0xb868
+#define HAWKEYE_OMAP36XX       0xb891
+
+#define HAWKEYE_SHIFT          12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX           0x3400  /* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX             0x3500  /* AM35xx devices          */
+#define CPU_OMAP36XX           0x3600  /* OMAP36xx devices        */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503               0x5c00
+#define OMAP3515               0x1c00
+#define OMAP3525               0x4c00
+#define OMAP3530               0x0c00
+
+#define AM3505                 0x5c00
+#define AM3517                 0x1c00
+
+#define OMAP3730               0x0c00
+
+/*
+ * ROM code API related flags
+ */
+#define OMAP3_GP_ROMCODE_API_L2_INVAL          1
+#define OMAP3_GP_ROMCODE_API_WRITE_ACR         3
+
+/*
+ * EMU device PPA HAL related flags
+ */
+#define OMAP3_EMU_HAL_API_L2_INVAL             40
+#define OMAP3_EMU_HAL_API_WRITE_ACR            42
+
+#define OMAP3_EMU_HAL_START_HAL_CRITICAL       4
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME         30
+#define OMAP_ABB_CLOCK_CYCLES          8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK       (0x1 << 26)
+
 #endif