arm: omap: add support for am57xx devices

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 86d4711a14367b0a45ee9f0ed15292a4edd22a86..0dc584b8ce68a6d38ba8a711b68fa3bd7842652a 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -5,23 +5,7 @@
  *     Aneesh V <aneesh@ti.com>
  *     Sricharan R <r.sricharan@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _CLOCKS_OMAP5_H_
 #define _CLOCKS_OMAP5_H_
@@ -81,7 +65,7 @@
 #define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
 /* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 /* CM_CLKSEL_CORE */
 #define CLKSEL_CORE_SHIFT      0
@@ -98,6 +82,12 @@
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK    0
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK    1
 
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT     0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK      1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1          0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2          1
+
 /* CM_BYPCLK_DPLL_IVA */
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT                0
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK         3
@@ -147,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK              (1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK          (1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK            (1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK           (1 << 24)
 
@@ -159,6 +152,33 @@
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK  8
 
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK                  (1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK              (1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK              (1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK               (1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK               (1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK                  (1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK                  (1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK                  (1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK              (1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK               (1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE   (1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE   (1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE   (1 << 10)
+
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K   (1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW   (1 << 0)
+#define OPTFCLKEN_REFCLK960M                   (1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
+
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK  (3 << 24)
@@ -185,6 +205,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET      (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
 #define SMPS_REG_ADDR_12_MPU   0x23
@@ -254,11 +278,11 @@
 
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR               0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU          0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE          0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU           0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE          0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA           0x37
+#define TPS659038_REG_ADDR_SMPS12              0x23
+#define TPS659038_REG_ADDR_SMPS45              0x2B
+#define TPS659038_REG_ADDR_SMPS6               0x2F
+#define TPS659038_REG_ADDR_SMPS7               0x33
+#define TPS659038_REG_ADDR_SMPS8               0x37
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60
@@ -275,6 +299,11 @@
 #define TPS62361_BASE_VOLT_MV  500
 #define TPS62361_VSEL0_GPIO    7
 
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0           0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ       1000
+
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
@@ -285,11 +314,27 @@
  */
 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC        31219
 
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 #define V_OSCK                 20000000        /* Clock output from T2 */
 #else
 #define V_OSCK                 19200000        /* Clock output from T2 */
 #endif
 
 #define V_SCLK V_OSCK
+
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK      (1 << 28)
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK             (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT         1
+#define AUXCLK_SRCSELECT_MASK          (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT            16
+#define AUXCLK_CLKDIV_MASK             (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK       0
+#define AUXCLK_SRCSELECT_CORE_DPLL     1
+#define AUXCLK_SRCSELECT_PER_DPLL      2
+#define AUXCLK_SRCSELECT_ALTERNATE     3
+
 #endif /* _CLOCKS_OMAP5_H_ */