Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index a91da7d7875198eb9c8cc5ff0699a5db8bdd712a..b632635d3e73d742164540e4362f828adb0cb885 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -57,7 +57,10 @@
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0         0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
 #define OMAP5432_CONTROL_ID_CODE_ES1_0         0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
+#define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
 
 /* STD_FUSE_PROD_ID_1 */
 #define STD_FUSE_PROD_ID_1             (CTRL_BASE + 0x218)
@@ -166,6 +169,12 @@ struct s32ktimer {
 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE                         0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
 
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100
@@ -221,7 +230,26 @@ struct s32ktimer {
 #define CH_FLAGS_CHFLASH       (0x1 << 2)
 #define CH_FLAGS_CHMMCSD       (0x1 << 3)
 
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT              30
+#define OVERRIDE_XS_MASK               (1 << 30)
+#define SRCODE_READ_XS_SHIFT           12
+#define SRCODE_READ_XS_MASK            (0xff << 12)
+#define PWRDWN_XS_SHIFT                        11
+#define PWRDWN_XS_MASK                 (1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT         4
+#define DIVIDE_FACTOR_XS_MASK          (0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT       1
+#define MULTIPLY_FACTOR_XS_MASK                (0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT   0
+#define SRCODE_OVERRIDE_SEL_XS_MASK    (1 << 0)
+
 #ifndef __ASSEMBLY__
+struct srcomp_params {
+       s8 divide_factor;
+       s8 multiply_factor;
+};
+
 struct omap_boot_parameters {
        char *boot_message;
        unsigned int mem_boot_descriptor;
@@ -229,5 +257,15 @@ struct omap_boot_parameters {
        unsigned char reset_reason;
        unsigned char ch_flags;
 };
+
+struct ctrl_ioregs {
+       u32 ctrl_ddrch;
+       u32 ctrl_lpddr2ch;
+       u32 ctrl_ddr3ch;
+       u32 ctrl_ddrio_0;
+       u32 ctrl_ddrio_1;
+       u32 ctrl_ddrio_2;
+       u32 ctrl_emif_sdram_config_ext;
+};
 #endif /* __ASSEMBLY__ */
 #endif