/*
* MXS DMA channels
*/
-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)
enum {
MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_MX6)
+#elif defined(CONFIG_SOC_MX6)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
unsigned int pending_num;
struct list_head active;
struct list_head done;
+ unsigned long timeout;
};
struct mxs_dma_desc *mxs_dma_desc_alloc(void);
void mxs_dma_desc_free(struct mxs_dma_desc *);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+int mxs_dma_set_timeout(int channel, unsigned long timeout);
+unsigned long mxs_dma_get_timeout(int channel);
int mxs_dma_go(int chan);
void mxs_dma_init(void);