*
* Aneesh V <aneesh@ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
+ u32 cm_clkmode_dpll_gmac;
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
u32 cm_div_m2_dpll_unipro;
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
+ u32 cm_coreaon_usb_phy1_core_clkctrl;
+ u32 cm_coreaon_usb_phy2_core_clkctrl;
+ u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
u32 cm_l3init_hsusbotg_clkctrl;
u32 cm_l3init_hsusbtll_clkctrl;
u32 cm_l3init_p1500_clkctrl;
+ u32 cm_l3init_sata_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
+ u32 cm_l3init_ocp2scp3_clkctrl;
+ u32 cm_l3init_usb_otg_ss1_clkctrl;
+ u32 cm_l3init_usb_otg_ss2_clkctrl;
u32 prm_irqstatus_mpu_2;
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
u32 prm_rstctrl;
u32 prm_rstst;
u32 prm_rsttime;
+ u32 prm_io_pmctrl;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
- u32 prm_sldo_core_setup;
- u32 prm_sldo_core_ctrl;
- u32 prm_sldo_mpu_setup;
- u32 prm_sldo_mpu_ctrl;
- u32 prm_sldo_mm_setup;
- u32 prm_sldo_mm_ctrl;
u32 prm_abbldo_mpu_setup;
u32 prm_abbldo_mpu_ctrl;
/* SCRM stuff, used by some boards */
u32 scrm_auxclk0;
u32 scrm_auxclk1;
+
+ /* GMAC Clk Ctrl */
+ u32 cm_gmac_gmac_clkctrl;
+ u32 cm_gmac_clkstctrl;
+
+ /* IPU */
+ u32 cm_ipu_clkstctrl;
+ u32 cm_ipu_i2c5_clkctrl;
+
+ /*l3main1 edma*/
+ u32 cm_l3main1_tptc1_clkctrl;
+ u32 cm_l3main1_tptc2_clkctrl;
};
struct omap_sys_ctrl_regs {
u32 control_status;
+ u32 control_core_mac_id_0_lo;
+ u32 control_core_mac_id_0_hi;
+ u32 control_core_mac_id_1_lo;
+ u32 control_core_mac_id_1_hi;
u32 control_std_fuse_opp_vdd_mpu_2;
+ u32 control_phy_power_usb;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_core_mmr_lock3;
u32 control_core_control_io1;
u32 control_core_control_io2;
u32 control_id_code;
+ u32 control_std_fuse_die_id_0;
+ u32 control_std_fuse_die_id_1;
+ u32 control_std_fuse_die_id_2;
+ u32 control_std_fuse_die_id_3;
u32 control_std_fuse_opp_bgap;
u32 control_ldosram_iva_voltage_ctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_usbotghs_ctrl;
+ u32 control_phy_power_sata;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
u32 control_efuse_12;
u32 control_efuse_13;
u32 control_padconf_wkup_base;
+ u32 iodelay_config_base;
+ u32 ctrl_core_sma_sw_0;
+ u32 ctrl_core_sma_sw_1;
};
struct dpll_params {
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
+ const struct dpll_params *gmac;
};
struct pmic_data {
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038;
+
void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
u32 const *clk_modules_explicit_en,
u8 wait_for_enable);
+void do_disable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_disable,
+ u8 wait_for_disable);
+
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
u32 omap_ddr_clk(void);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
+
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
-/* HW Init Context */
-#define OMAP_INIT_CONTEXT_SPL 0
-#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
-#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
-#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
+void usb_fake_mac_from_die_id(u32 *id);
+void usb_set_serial_num_from_die_id(u32 *id);
+void recalibrate_iodelay(void);
+
+void omap_smc1(u32 service, u32 val);
+
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
return *omap_si_rev;
}
+#define OMAP44xx 0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
#define OMAP54xx 0x54000000
static inline u8 is_omap54xx(void)
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
}
+
+#define DRA7XX 0x07000000
+#define DRA72X 0x07200000
+
+static inline u8 is_dra7xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
+
+static inline u8 is_dra72x(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFFF00000) == DRA72X;
+}
#endif
/*
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
+#define OMAP4470_ES1_0 0x44700100
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
+#define DRA752_ES1_1 0x07520110
+#define DRA752_ES2_0 0x07520200
+#define DRA722_ES1_0 0x07220100
/*
* SRAM scratch space entries
#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+/* Boot parameters */
+#define DEVICE_DATA_OFFSET 0x18
+#define BOOT_MODE_OFFSET 0x8
+
+#define CH_FLAGS_CHSETTINGS (1 << 0)
+#define CH_FLAGS_CHRAM (1 << 1)
+#define CH_FLAGS_CHFLASH (1 << 2)
+#define CH_FLAGS_CHMMCSD (1 << 3)
+
+#ifndef __ASSEMBLY__
+u32 omap_sys_boot_device(void);
+#endif
+
#endif /* _OMAP_COMMON_H_ */
projects / karo-tx-uboot.git / blobdiff