arm: Move tlb_addr and tlb_size to arch_global_data

[karo-tx-uboot.git] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1cab27c22629fe5bd034d8278efa8d09e36f7378..b6e5e95530b3793f0be70289eb53ed7207cb305b 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -46,7 +46,7 @@ static void cp_delay (void)
 
 void set_section_dcache(int section, enum dcache_option option)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 *page_table = (u32 *)gd->arch.tlb_addr;
        u32 value;
 
        value = (section << MMU_SECTION_SHIFT) | (3 << 10);
@@ -65,7 +65,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void mmu_set_region_dcache_behaviour(u32 start, int size,
                                     enum dcache_option option)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 *page_table = (u32 *)gd->arch.tlb_addr;
        u32 upto, end;
 
        end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -111,7 +111,7 @@ static inline void mmu_setup(void)
 
        /* Copy the page table address to cp15 */
        asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (gd->tlb_addr) : "memory");
+                    : : "r" (gd->arch.tlb_addr) : "memory");
        /* Set the access control to all-supervisor */
        asm volatile("mcr p15, 0, %0, c3, c0, 0"
                     : : "r" (~0));