Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d9175f058327fabf4f91ee0d751a043e4b0c0133..939de10e039153d0fd1ef29cb962366d5357a355 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/system.h>
 
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 #define CACHE_SETUP    0x1a
@@ -34,6 +34,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void __arm_init_before_mmu(void)
+{
+}
+void arm_init_before_mmu(void)
+       __attribute__((weak, alias("__arm_init_before_mmu")));
+
 static void cp_delay (void)
 {
        volatile int i;
@@ -65,6 +71,7 @@ static inline void mmu_setup(void)
        int i;
        u32 reg;
 
+       arm_init_before_mmu();
        /* Set up an identity-mapping for all 4GB, rw for everyone */
        for (i = 0; i < 4096; i++)
                page_table[i] = i << 20 | (3 << 10) | 0x12;
@@ -85,13 +92,18 @@ static inline void mmu_setup(void)
        set_cr(reg | CR_M);
 }
 
+static int mmu_enabled(void)
+{
+       return get_cr() & CR_M;
+}
+
 /* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
        uint32_t reg;
 
        /* The data cache is not active unless the mmu is enabled too */
-       if (cache_bit == CR_C)
+       if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
        cp_delay();
@@ -103,22 +115,22 @@ static void cache_disable(uint32_t cache_bit)
 {
        uint32_t reg;
 
+       reg = get_cr();
+       cp_delay();
+
        if (cache_bit == CR_C) {
                /* if cache isn;t enabled no need to disable */
-               reg = get_cr();
                if ((reg & CR_C) != CR_C)
                        return;
                /* if disabling data cache, disable mmu too */
                cache_bit |= CR_M;
-               flush_cache(0, ~0);
+               flush_dcache_all();
        }
-       reg = get_cr();
-       cp_delay();
        set_cr(reg & ~cache_bit);
 }
 #endif
 
-#ifdef CONFIG_SYS_NO_ICACHE
+#ifdef CONFIG_SYS_ICACHE_OFF
 void icache_enable (void)
 {
        return;
@@ -150,7 +162,7 @@ int icache_status(void)
 }
 #endif
 
-#ifdef CONFIG_SYS_NO_DCACHE
+#ifdef CONFIG_SYS_DCACHE_OFF
 void dcache_enable (void)
 {
        return;