Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / arch / arm / lib / cache-cp15.c

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e6c3eae6f9d2dad1b0bfe2f73d58922439870afa..a69c5f6649df904e1c447405749de6e02b13546e 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -20,7 +20,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <common.h>
 #include <asm/system.h>
 
@@ -40,16 +39,6 @@ void __arm_init_before_mmu(void)
 void arm_init_before_mmu(void)
        __attribute__((weak, alias("__arm_init_before_mmu")));
 
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++)
-               nop();
-       asm volatile("" : : : "memory");
-}
-
 static inline void dram_bank_mmu_setup(int bank)
 {
        u32 *page_table = (u32 *)gd->tlb_addr;
@@ -80,15 +69,16 @@ static inline void mmu_setup(void)
                dram_bank_mmu_setup(i);
        }
 
-       /* Copy the page table address to cp15 */
-       asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (page_table) : "memory");
-       /* Set the access control to all-supervisor */
-       asm volatile("mcr p15, 0, %0, c3, c0, 0"
-                    : : "r" (~0));
+       asm volatile(
+               /* Copy the page table address to cp15 */
+               "mcr p15, 0, %0, c2, c0, 0\n"
+               /* Set the access control to all-supervisor */
+               "mcr p15, 0, %1, c3, c0, 0\n"
+               :
+               : "r"(page_table), "r"(~0)
+               );
        /* and enable the mmu */
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | CR_M);
 }
 
@@ -106,7 +96,6 @@ static void cache_enable(uint32_t cache_bit)
        if ((cache_bit == CR_C) && !mmu_enabled())
                mmu_setup();
        reg = get_cr(); /* get control reg. */
-       cp_delay();
        set_cr(reg | cache_bit);
 }
 
@@ -125,7 +114,6 @@ static void cache_disable(uint32_t cache_bit)
                flush_dcache_all();
        }
        reg = get_cr();
-       cp_delay();
        set_cr(reg & ~cache_bit);
 }
 #endif