ARM: keystone2: Use common definition for clk_get_rate

[karo-tx-uboot.git] / arch / arm / mach-keystone / include / mach / clock-k2l.h

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4dcf3bca5b7310082fe374a1de9c629e3e..8772a7dcb15a6b2eb51937e090ee3fb45e87a7cf 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,64 +10,10 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-enum ext_clk_e {
-       sys_clk,
-       alt_core_clk,
-       pa_clk,
-       tetris_clk,
-       ddr3_clk,
-       pcie_clk,
-       sgmii_clk,
-       usb_clk,
-       rp1_clk,
-       ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
-       CLK(0, core_pll_clk)\
-       CLK(1, pass_pll_clk)\
-       CLK(2, tetris_pll_clk)\
-       CLK(3, ddr3_pll_clk)\
-       CLK(4, sys_clk0_clk)\
-       CLK(5, sys_clk0_1_clk)\
-       CLK(6, sys_clk0_2_clk)\
-       CLK(7, sys_clk0_3_clk)\
-       CLK(8, sys_clk0_4_clk)\
-       CLK(9, sys_clk0_6_clk)\
-       CLK(10, sys_clk0_8_clk)\
-       CLK(11, sys_clk0_12_clk)\
-       CLK(12, sys_clk0_24_clk)\
-       CLK(13, sys_clk1_clk)\
-       CLK(14, sys_clk1_3_clk)\
-       CLK(15, sys_clk1_4_clk)\
-       CLK(16, sys_clk1_6_clk)\
-       CLK(17, sys_clk1_12_clk)\
-       CLK(18, sys_clk2_clk)\
-       CLK(19, sys_clk3_clk)\
-
 #define PLLSET_CMD_LIST        "<pa|arm|ddr3>"
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       TETRIS_PLL,
-       DDR3_PLL,
-};
-
-enum {
-       SPD800,
-       SPD1000,
-       SPD1200,
-       SPD1350,
-       SPD1400,
-       SPD_RSV
-};
-
 #define CORE_PLL_799   {CORE_PLL, 13, 1, 2}
 #define CORE_PLL_983   {CORE_PLL, 16, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 114, 7, 2}
@@ -92,4 +38,9 @@ enum {
 #define DDR3_PLL_800   {DDR3_PLL, 16, 1, 2}
 #define DDR3_PLL_333   {DDR3_PLL, 20, 1, 6}
 
+/* k2l DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS   0x383
+/* k2l ARM supportd 800, 1000, 1200, MHz */
+#define ARM_SUPPORTED_SPEEDS   0x383
+
 #endif