arm64: mvebu: Add support for the Marvell Armada 3700 SoC

[karo-tx-uboot.git] / arch / arm / mach-mvebu / include / mach / soc.h

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index b31794036691e4f6e0f6aa7e071682c02b5c8c65..063d6ccabd88e983e81483de499b6c75b27f699c 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -14,10 +14,14 @@
 #define SOC_MV78230_ID         0x7823
 #define SOC_MV78260_ID         0x7826
 #define SOC_MV78460_ID         0x7846
+#define SOC_88F6720_ID         0x6720
 #define SOC_88F6810_ID         0x6810
 #define SOC_88F6820_ID         0x6820
 #define SOC_88F6828_ID         0x6828
 
+/* A375 revisions */
+#define MV_88F67XX_A0_ID       0x3
+
 /* A38x revisions */
 #define MV_88F68XX_Z1_ID       0x0
 #define MV_88F68XX_A0_ID       0x4
@@ -33,7 +37,7 @@
 /* SOC specific definations */
 #define INTREG_BASE            0xd0000000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
 /*
  * The SPL U-Boot version still runs with the default
  * address for the internal registers, configured by
@@ -51,6 +55,7 @@
 #define MVEBU_L2_CACHE_BASE    (MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE  MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE                (MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE       (MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE         (MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE       (MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE       (MVEBU_REGISTER(0x18140))
@@ -68,6 +73,7 @@
 #define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE                (MVEBU_REGISTER(0xd8000))
 #define MVEBU_LCD_BASE         (MVEBU_REGISTER(0xe0000))
+#define MVEBU_DFX_BASE         (MVEBU_REGISTER(0xe4000))
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG  (MVEBU_REGISTER(0x20200))
 #define MBUS_ERR_PROP_EN       (1 << 8)
@@ -87,6 +93,7 @@
 #define SPI_PUP_EN             BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)     (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
 #define NAND_ECC_DIVCKL_RATIO_OFFS     8
 #define NAND_ECC_DIVCKL_RATIO_MASK     (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
 
@@ -106,7 +113,20 @@
 #define BOOTROM_ERR_MODE_MASK  (0xf << BOOTROM_ERR_MODE_OFFS)
 #define BOOTROM_ERR_MODE_UART  0x6
 
-#if defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375)
+/* SAR values for Armada 375 */
+#define CONFIG_SAR_REG         (MVEBU_REGISTER(0xe8200))
+#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0xe8204))
+
+#define SAR_CPU_FREQ_OFFS      17
+#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      3
+#define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART         0x30
+#define BOOT_FROM_SPI          0x38
+#elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
 #define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))