Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / blackfin / cpu / cpu.c

diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 18dbdf7abe9686b6e5220b534b5c3aa13bdbf2bb..2409c300ed1441e6660fbd8475ae3e5ee01023f4 100644 (file)
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -16,12 +16,38 @@
 #include <asm/mach-common/bits/core.h>
 #include <asm/mach-common/bits/ebiu.h>
 #include <asm/mach-common/bits/trace.h>
+#include <asm/serial.h>
 
 #include "cpu.h"
-#include "serial.h"
+#include "initcode.h"
 
 ulong bfin_poweron_retx;
 
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+void bfin_core1_start(void)
+{
+#ifdef BF561_FAMILY
+       /* Enable core 1 */
+       bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
+#else
+       /* Enable core 1 */
+       bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
+       bfin_write32(RCU0_CRCTL, 0);
+
+       bfin_write32(RCU0_CRCTL, 0x2);
+
+       /* Check if core 1 starts */
+       while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
+               continue;
+
+       bfin_write32(RCU0_CRCTL, 0);
+
+       /* flag to notify cces core 1 application */
+       bfin_write32(SDU0_MSG_SET, (1 << 19));
+#endif
+}
+#endif
+
 __attribute__ ((__noreturn__))
 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 {
@@ -44,13 +70,16 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
                extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
                memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
        }
-#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-       /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
-        * after it has finished loading the LDR.  So configure it again.
+
+       /*
+        * Make sure our async settings are committed.  Some bootroms
+        * (like the BF537) will reset some registers on us after it
+        * has finished loading the LDR.  Or if we're booting over
+        * JTAG, the initcode never got a chance to run.  Or if we
+        * aren't booting from parallel flash, the initcode skipped
+        * this step completely.
         */
-       else
-               bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
+       program_async_controller(NULL);
 
        /* Save RETX so we can pass it while booting Linux */
        bfin_poweron_retx = bootflag;
@@ -64,11 +93,20 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
        /* Reset upon a double exception rather than just hanging.
         * Do not do bfin_read on SWRST as that will reset status bits.
         */
+# ifdef SWRST
        bfin_write_SWRST(DOUBLE_FAULT);
+# endif
+#endif
+
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+       bfin_core1_start();
 #endif
 
        serial_early_puts("Board init flash\n");
        board_init_f(bootflag);
+
+       /* should not be reached */
+       while (1);
 }
 
 int exception_init(void)
@@ -88,7 +126,7 @@ int irq_init(void)
 #elif defined(SICA_IMASK0)
        bfin_write_SICA_IMASK0(0);
        bfin_write_SICA_IMASK1(0);
-#else
+#elif defined(SIC_IMASK)
        bfin_write_SIC_IMASK(0);
 #endif
        /* Set up a dummy NMI handler if needed.  */