--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF609_proc__
+#define __BFIN_DEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
+#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
+#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
+#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
+#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
+#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
+#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
+#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
+#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
+#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
+#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
+#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
+#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
+#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
+#define RSI_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
+#define RSI_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
+#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */
+#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
+#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Ack Timeout Register */
+#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
+#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
+#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
+#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
+#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
+#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
+#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
+#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Id Register */
+#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Id Register */
+#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Id Register */
+#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Id Register */
+
+#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
+#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
+
+#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
+#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
+#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
+#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
+#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
+#define UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */
+#define UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
+#define UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
+#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
+#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
+#define UART0_TAIP 0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */
+#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
+#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
+#define UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */
+#define UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */
+#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
+#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
+#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
+#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
+#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
+#define UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */
+#define UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
+#define UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
+#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
+#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
+#define UART1_TAIP 0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */
+#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
+#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
+#define UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */
+#define UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */
+
+#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable */
+#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set */
+#define PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear */
+#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control */
+#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable */
+#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set */
+#define PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear */
+#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control */
+#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable */
+#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set */
+#define PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear */
+#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control */
+#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable */
+#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set */
+#define PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear */
+#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control */
+#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable */
+#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set */
+#define PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear */
+#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control */
+#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable */
+#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set */
+#define PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear */
+#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control */
+#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable */
+#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set */
+#define PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear */
+#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control */
+
+#define SMC_GCTL 0xFFC16004 /* SMC Control Register */
+#define SMC_GSTAT 0xFFC16008 /* SMC Status Register */
+#define SMC_B0CTL 0xFFC1600C /* SMC Bank0 Control Register */
+#define SMC_B0TIM 0xFFC16010 /* SMC Bank0 Timing Register */
+#define SMC_B0ETIM 0xFFC16014 /* SMC Bank0 Extended Timing Register */
+#define SMC_B1CTL 0xFFC1601C /* SMC BANK1 Control Register */
+#define SMC_B1TIM 0xFFC16020 /* SMC BANK1 Timing Register */
+#define SMC_B1ETIM 0xFFC16024 /* SMC BANK1 Extended Timing Register */
+#define SMC_B2CTL 0xFFC1602C /* SMC BANK2 Control Register */
+#define SMC_B2TIM 0xFFC16030 /* SMC BANK2 Timing Register */
+#define SMC_B2ETIM 0xFFC16034 /* SMC BANK2 Extended Timing Register */
+#define SMC_B3CTL 0xFFC1603C /* SMC BANK3 Control Register */
+#define SMC_B3TIM 0xFFC16040 /* SMC BANK3 Timing Register */
+#define SMC_B3ETIM 0xFFC16044 /* SMC BANK3 Extended Timing Register */
+
+#define WDOG_CTL 0xFFC17000 /* WDOG0 Control Register */
+#define WDOG_CNT 0xFFC17004 /* WDOG0 Count Register */
+#define WDOG_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
+#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
+#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
+#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
+
+#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
+#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
+
+#define SPI0_REGBASE 0xFFC40400 /* SPI0 Base Address */
+#define SPI1_REGBASE 0xFFC40500 /* SPI1 Base Address */
+
+#define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
+#define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */
+#define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */
+#define DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
+#define DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */
+#define DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value */
+#define DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment */
+#define DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
+#define DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Desc Pointer */
+#define DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */
+#define DMA10_STAT 0xFFC05030 /* DMA10 Status Register */
+#define DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/
+#define DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Curr Row Count (2D only) */
+#define DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
+#define DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
+#define DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
+#define DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/
+
+#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
+#define DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Desc */
+#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
+#define DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Desc */
+
+#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
+#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
+#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
+#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
+#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
+#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
+#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
+#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
+#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
+#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
+#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
+#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
+#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
+#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
+#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
+#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
+#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
+
+#define SEC0_CCTL0 0xFFCA4400 /* SEC0 Core Control Register n */
+#define SEC0_CCTL1 0xFFCA4440 /* SEC0 Core Control Register n */
+#define SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */
+#define SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */
+#define SEC0_SCTL0 0xFFCA4800 /* SEC0 IRQ Source Control Register n */
+
+#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
+#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
+#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
+#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
+#define RCU0_SIDIS 0xFFCA6010 /* RCU0 Sys Interface Disable Register */
+#define RCU0_SISTAT 0xFFCA6014 /* RCU0 Sys Interface Status Register */
+#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
+#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
+#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
+#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
+
+#define CGU_CTL 0xFFCA8000 /* CGU0 Control Register */
+#define CGU_STAT 0xFFCA8004 /* CGU0 Status Register */
+#define CGU_DIV 0xFFCA8008 /* CGU0 Divisor Register */
+#define CGU_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
+
+#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
+#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
+#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable */
+#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable */
+#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status */
+#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */
+#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable */
+#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
+#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
+#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
+#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
+#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
+#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
+#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
+#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
+#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
+#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
+#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
+#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
+#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
+#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
+#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
+#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
+#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
+#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
+#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
+#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
+#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
+
+#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode*/
+#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
+#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
+#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
+#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
+
+
+#define CHIPID 0xffc00014
+/* CHIPID Masks */
+#define CHIPID_VERSION 0xF0000000
+#define CHIPID_FAMILY 0x0FFFF000
+#define CHIPID_MANUFACTURE 0x00000FFE
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE 0x8000
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE 0x4000
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */
+#define L1_INST_SRAM_SIZE 0x8000
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#define COREB_L1_CODE_START 0xFF600000
+
+#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
projects / karo-tx-uboot.git / blobdiff