MIPS: start.S: set sp register directly

[karo-tx-uboot.git] / arch / mips / cpu / mips64 / start.S

diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 4112de7026a51f8c854a14414f9d9f920b7ef28f..d3c5ceaffd4e8a5aa2aedf08331e9bc07429d1b9 100644 (file)
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -108,7 +108,12 @@ reset:
        mtc0    t0, CP0_CONFIG
 #endif
 
-       /* Initialize $gp */
+       /*
+        * Initialize $gp, force 8 byte alignment of bal instruction to forbid
+        * the compiler to put nop's between bal and _gp. This is required to
+        * keep _gp and ra aligned to 8 byte.
+        */
+       .align  3
        bal     1f
         nop
        .dword  _gp
@@ -132,8 +137,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       dli     t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       dla     sp, 0(t0)
+       dli     sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        dla     t9, board_init_f
        jr      t9
@@ -187,7 +191,7 @@ relocate_code:
        lw      t3, 0(t0)
        sw      t3, 0(t1)
        daddu   t0, 4
-       ble     t0, t2, 1b
+       blt     t0, t2, 1b
         daddu  t1, 4
 
        /* If caches were enabled, we would have to flush them here. */
@@ -254,3 +258,4 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop