Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / arch / mips / cpu / xburst / cpu.c

diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa47c93f858d7a68f6fb9812ed35cb57636..1fdaa32bb087c251b11e54f1ae4fa46af321622e 100644 (file)
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -4,23 +4,7 @@
  * (C) Copyright 2011
  * Xiangfu Liu <xiangfu@openmobilefree.net>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -84,8 +68,8 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
        }
 }
 
@@ -96,7 +80,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
 }
 
 void flush_icache_all(void)
@@ -118,7 +102,7 @@ void flush_icache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Store_Tag_I, addr);
+               cache_op(INDEX_STORE_TAG_I, addr);
        }
 
        /* invalidate btb */
@@ -139,7 +123,7 @@ void flush_dcache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Writeback_Inv_D, addr);
+               cache_op(INDEX_WRITEBACK_INV_D, addr);
        }
 
        __asm__ __volatile__("sync");