Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / arch / nds32 / cpu / n1213 / ag102 / cpu.c

diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
index ed88b522a492ad3bcfb2197ee1a1e880b3b57554..252b69db7c30d7aa16ea76c143b74b61f4228766 100644 (file)
--- a/arch/nds32/cpu/n1213/ag102/cpu.c
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        /*NOTREACHED*/
 }
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
-       if (cache == ICACHE)
-               return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
-                                       >> ICM_CFG_OFF_ISZ) - 1);
-       else
-               return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
-                                       >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(DCACHE);
-
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(ICACHE);
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-       dcache_flush_range(addr, addr + size);
-       icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x01\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void icache_disable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x01\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int icache_status(void)
-{
-       int ret;
-
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0,  $p0, 0x01\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-       );
-
-        return ret;
-}
-
-void dcache_enable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x02\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void dcache_disable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x02\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int dcache_status(void)
-{
-       int ret;
-
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0, $p0, 0x02\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-        );
-
-        return ret;
-}