* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
+#ifndef CONFIG_NAND_SPL
.globl icache_enable
icache_enable:
mfspr r3, HID0
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
+#endif /* !CONFIG_NAND_SPL */
.globl dcache_enable
dcache_enable: