board/b4860qds: Add support to make Aurora work on B4860QDS

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / b4860_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 9990202f421af77c459f2810b340af4bfb8c879d..c96ad0b486ebca24a8f56b693bedf1cec9483d0d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -31,8 +15,27 @@ struct serdes_config {
        u8 lanes[SRDS_MAX_LANES];
 };
 
+#ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
+       {0x02, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x04, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x05, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x06, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x08, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x09, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
        {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
                CPRI4, CPRI3, CPRI2, CPRI1}},
        {0x0E, {CPRI8, CPRI7,   CPRI6, CPRI5,
@@ -41,6 +44,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
                CPRI4, CPRI3, CPRI2, CPRI1}},
        {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
        {0x30, {AURORA, AURORA,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -53,8 +62,22 @@ static struct serdes_config serdes1_cfg_tbl[] = {
        {0x34, {AURORA, AURORA,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x39, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
        {0x3E, {CPRI8, CPRI7,   CPRI6, CPRI5,
                CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x5C, {AURORA, AURORA,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
+       {0x5D, {AURORA, AURORA,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               CPRI4, CPRI3, CPRI2, CPRI1} },
        {}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
@@ -84,6 +107,8 @@ static struct serdes_config serdes2_cfg_tbl[] = {
        {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, AURORA,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
        {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SRIO2, SRIO2, AURORA, AURORA,
                XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -94,6 +119,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
                SRIO2, SRIO2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                XFI_FM1_MAC9, XFI_FM1_MAC10}},
+       {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               XFI_FM1_MAC9, XFI_FM1_MAC10}},
        {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                XAUI_FM1_MAC10, XAUI_FM1_MAC10,
@@ -111,8 +139,56 @@ static struct serdes_config serdes2_cfg_tbl[] = {
        {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+       {}
+};
+#endif
+
+#ifdef CONFIG_PPC_B4420
+static struct serdes_config serdes1_cfg_tbl[] = {
+       {0x0D, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x0E, {NONE, NONE, CPRI8, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x0F, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x18, {NONE, NONE,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x1B, {NONE, NONE,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x1E, {NONE, NONE, AURORA, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x21, {NONE, NONE, AURORA, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x3E, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
        {}
 };
+static struct serdes_config serdes2_cfg_tbl[] = {
+       {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               AURORA, AURORA, NONE, NONE, NONE, NONE} },
+       {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               AURORA, AURORA, NONE, NONE, NONE, NONE} },
+       {0x9A, {PCIE1, PCIE1,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+               NONE, NONE, NONE, NONE} },
+       {}
+};
+#endif
+
 static struct serdes_config *serdes_cfg_tbl[] = {
        serdes1_cfg_tbl,
        serdes2_cfg_tbl,