Merge branch 'karo-tx-uboot' into kc-merge

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index b77964a4c795a6f9f6e17e750843b5492be08f4e..3d6ec843df3f156b7961975f6931552c434cb2ad 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -17,12 +17,12 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
 #include <post.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,6 +77,30 @@ int checkcpu (void)
        major = SVR_MAJ(svr);
        minor = SVR_MIN(svr);
 
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+       if (SVR_SOC_VER(svr) == SVR_T4080) {
+               ccsr_rcpm_t *rcpm =
+                       (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+               setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+                            FSL_CORENET_DEVDISR2_DTSEC1_9);
+               setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+               setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+               /* It needs SW to disable core4~7 as HW design sake on T4080 */
+               for (i = 4; i < 8; i++)
+                       cpu_disable(i);
+
+               /* request core4~7 into PH20 state, prior to entering PCL10
+                * state, all cores in cluster should be placed in PH20 state.
+                */
+               setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+               /* put the 2nd cluster into PCL10 state */
+               setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+       }
+#endif
+
        if (cpu_numcores() > 1) {
 #ifndef CONFIG_MP
                puts("Unicore software on multiprocessor system!!\n"
@@ -130,6 +154,11 @@ int checkcpu (void)
 
        get_sys_info(&sysinfo);
 
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+       if (sysinfo.diff_sysclk == 1)
+               puts("Single Source Clock Configuration\n");
+#endif
+
        puts("Clock Configuration:");
        for_each_cpu(i, core, nr_cores, mask) {
                if (!(i & 3))
@@ -210,7 +239,7 @@ int checkcpu (void)
        printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
 #endif
 
-       puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
+       puts("L1:    D-cache 32 KiB enabled\n       I-cache 32 KiB enabled\n");
 
 #ifdef CONFIG_FSL_CORENET
        /* Display the RCW, so that no one gets confused as to what RCW
@@ -272,7 +301,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
 #define CONFIG_SYS_FSL_TBCLK_DIV 8
 #endif
-unsigned long get_tbclk (void)
+__weak unsigned long get_tbclk (void)
 {
        unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
 
@@ -281,6 +310,14 @@ unsigned long get_tbclk (void)
 
 
 #if defined(CONFIG_WATCHDOG)
+#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
+void
+init_85xx_watchdog(void)
+{
+       mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
+             TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+}
+
 void
 reset_85xx_watchdog(void)
 {
@@ -338,7 +375,8 @@ void mpc85xx_reginfo(void)
        !defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
+       defined(CONFIG_QEMU_E500)
        return fsl_ddr_sdram_size();
 #else
        return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
@@ -403,7 +441,7 @@ phys_size_t initdram(int board_type)
 
 /* Board-specific functions defined in each board's ddr.c */
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
-       unsigned int ctrl_num);
+       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
                       phys_addr_t *rpn);
 unsigned int
@@ -416,12 +454,12 @@ static void dump_spd_ddr_reg(void)
        int i, j, k, m;
        u8 *p_8;
        u32 *p_32;
-       ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+       struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
        generic_spd_eeprom_t
                spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
 
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
-               fsl_ddr_get_spd(spd[i], i);
+               fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
 
        puts("SPD data of all dimms (zero vaule is omitted)...\n");
        puts("Byte (hex)  ");
@@ -453,21 +491,21 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                switch (i) {
                case 0:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
                        break;
-#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
                case 1:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
                case 2:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
                case 3:
-                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                        break;
 #endif
                default:
@@ -482,7 +520,7 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
                printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
        puts("\n");
-       for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+       for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
                m = 0;
                printf("%6d (0x%04x)", k * 4, k * 4);
                for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {