Merge branch 'master' of git://git.denx.de/u-boot-x86

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ce59c2580a1ef83cb9b1cc00506ede9ad85e8953..df2ab6d73cbd73a3872c5263233483f3a277da41 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -42,36 +42,55 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Default board reset function
+ */
+static void
+__board_reset(void)
+{
+       /* Do nothing */
+}
+void board_reset(void) __attribute__((weak, alias("__board_reset")));
+
 int checkcpu (void)
 {
        sys_info_t sysinfo;
        uint pvr, svr;
-       uint fam;
        uint ver;
        uint major, minor;
        struct cpu_type *cpu;
        char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+       defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
-       u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-               >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+       /*
+        * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+        * mode. Previous platform use ddr ratio to do the same. This
+        * information is only for display here.
+        */
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       u32 ddr_sync = 0;       /* only async mode is supported */
+#else
        u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
                >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else  /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+       u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+               >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
        u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
-       int i;
+#endif /* CONFIG_FSL_CORENET */
+
+       unsigned int i, core, nr_cores = cpu_numcores();
+       u32 mask = cpu_mask();
 
        svr = get_svr();
        major = SVR_MAJ(svr);
-#ifdef CONFIG_MPC8536
-       major &= 0x7; /* the msb of this nibble is a mfg code */
-#endif
        minor = SVR_MIN(svr);
 
        if (cpu_numcores() > 1) {
@@ -85,7 +104,7 @@ int checkcpu (void)
                puts("CPU:   ");
        }
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        puts(cpu->name);
        if (IS_E_PROCESSOR(svr))
@@ -94,42 +113,45 @@ int checkcpu (void)
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
 
        pvr = get_pvr();
-       fam = PVR_FAM(pvr);
        ver = PVR_VER(pvr);
        major = PVR_MAJ(pvr);
        minor = PVR_MIN(pvr);
 
        printf("Core:  ");
-       if (PVR_FAM(PVR_85xx)) {
-               switch(PVR_MEM(pvr)) {
-               case 0x1:
-               case 0x2:
-                       puts("E500");
-                       break;
-               case 0x3:
-                       puts("E500MC");
-                       break;
-               case 0x4:
-                       puts("E5500");
-                       break;
-               default:
-                       puts("Unknown");
-                       break;
-               }
-       } else {
+       switch(ver) {
+       case PVR_VER_E500_V1:
+       case PVR_VER_E500_V2:
+               puts("E500");
+               break;
+       case PVR_VER_E500MC:
+               puts("E500MC");
+               break;
+       case PVR_VER_E5500:
+               puts("E5500");
+               break;
+       case PVR_VER_E6500:
+               puts("E6500");
+               break;
+       default:
                puts("Unknown");
+               break;
        }
 
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
+       if (nr_cores > CONFIG_MAX_CPUS) {
+               panic("\nUnexpected number of cores: %d, max is %d\n",
+                       nr_cores, CONFIG_MAX_CPUS);
+       }
+
        get_sys_info(&sysinfo);
 
        puts("Clock Configuration:");
-       for (i = 0; i < cpu_numcores(); i++) {
+       for_each_cpu(i, core, nr_cores, mask) {
                if (!(i & 3))
                        printf ("\n       ");
-               printf("CPU%d:%-4s MHz, ",
-                               i,strmhz(buf1, sysinfo.freqProcessor[i]));
+               printf("CPU%d:%-4s MHz, ", core,
+                       strmhz(buf1, sysinfo.freqProcessor[core]));
        }
        printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
@@ -176,6 +198,10 @@ int checkcpu (void)
        }
 #endif
 
+#if defined(CONFIG_FSL_IFC)
+       printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+#endif
+
 #ifdef CONFIG_CPM2
        printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
@@ -191,6 +217,10 @@ int checkcpu (void)
        }
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+#endif
+
 #ifdef CONFIG_SYS_DPAA_PME
        printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
 #endif
@@ -223,7 +253,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        mtspr(DBCR0,val);
 #else
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       out_be32(&gur->rstcr, 0x2);     /* HRESET_REQ */
+
+       /* Attempt board-specific reset */
+       board_reset();
+
+       /* Next try asserting HRESET_REQ */
+       out_be32(&gur->rstcr, 0x2);
        udelay(100);
 #endif
 
@@ -260,10 +295,7 @@ reset_85xx_watchdog(void)
        /*
         * Clear TSR(WIS) bit by writing 1
         */
-       unsigned long val;
-       val = mfspr(SPRN_TSR);
-       val |= TSR_WIS;
-       mtspr(SPRN_TSR, val);
+       mtspr(SPRN_TSR, TSR_WIS);
 }
 #endif /* CONFIG_WATCHDOG */
 
@@ -300,7 +332,8 @@ void mpc85xx_reginfo(void)
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
 #ifndef CONFIG_FSL_CORENET
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
+#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
+       !defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
@@ -358,7 +391,7 @@ phys_size_t initdram(int board_type)
        lbc_sdram_init();
 #endif
 
-       puts("DDR: ");
+       debug("DDR: ");
        return dram_size;
 }
 #endif /* CONFIG_SYS_RAMBOOT */
@@ -418,11 +451,21 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                switch (i) {
                case 0:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
                        break;
-#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
                case 1:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+               case 2:
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+               case 3:
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
                        break;
 #endif
                default: