powerpc/mpc85xx: Workaround for A-005812

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d5b17de7c678098076ed940215a6329fb7332c6b..48b38263fde213424eab2b2dcfe062a15bbb3fc8 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -7,23 +7,7 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -172,6 +156,9 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
                setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+               setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
+#endif
 
                out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
                /* Read back to sync write */
@@ -337,7 +324,7 @@ int enable_cluster_l2(void)
                        while ((in_be32(&l2cache->l2csr0)
                                & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
                                        ;
-                       out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE);
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
                }
                i++;
        } while (!(cluster & TP_CLUSTER_EOC));
@@ -412,6 +399,14 @@ int cpu_init_r(void)
                sync();
        }
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+       /*
+        * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
+        * in write shadow mode. Checking DCWS before setting SPR 976.
+        */
+       if (mfspr(L1CSR2) & L1CSR2_DCWS)
+               mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
+#endif
 
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
        spin = getenv("spin_table_compat");
@@ -545,8 +540,10 @@ skip_l2:
 
        enable_cpc();
 
+#ifndef CONFIG_SYS_FSL_NO_SERDES
        /* needs to be in ram since code uses global static vars */
        fsl_serdes_init();
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
        if (IS_SVR_REV(svr, 1, 0)) {
@@ -564,7 +561,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
        srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        char *s = getenv("bootmaster");
        if (s) {
                if (!strcmp(s, "SRIO1")) {